1/* $NetBSD: intel_display.c,v 1.26 2019/02/19 00:30:16 christos Exp $ */
2
3/*
4 * Copyright © 2006-2007 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: intel_display.c,v 1.26 2019/02/19 00:30:16 christos Exp $");
31
32#include <linux/dmi.h>
33#include <linux/module.h>
34#include <linux/input.h>
35#include <linux/i2c.h>
36#include <linux/kernel.h>
37#include <linux/slab.h>
38#include <linux/vgaarb.h>
39#include <linux/err.h>
40#include <linux/interrupt.h>
41#include <drm/drm_edid.h>
42#include <drm/drmP.h>
43#include "intel_drv.h"
44#include <drm/i915_drm.h>
45#include "i915_drv.h"
46#include "i915_trace.h"
47#include <drm/drm_atomic.h>
48#include <drm/drm_atomic_helper.h>
49#include <drm/drm_dp_helper.h>
50#include <drm/drm_crtc_helper.h>
51#include <drm/drm_plane_helper.h>
52#include <drm/drm_rect.h>
53#include <linux/dma_remapping.h>
54#include <linux/err.h>
55#include <asm/bug.h>
56#include <linux/math64.h>
57#include <linux/bitops.h>
58#include <linux/log2.h>
59
60/* Primary plane formats for gen <= 3 */
61static const uint32_t i8xx_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB1555,
65 DRM_FORMAT_XRGB8888,
66};
67
68/* Primary plane formats for gen >= 4 */
69static const uint32_t i965_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_XRGB2101010,
75 DRM_FORMAT_XBGR2101010,
76};
77
78static const uint32_t skl_primary_formats[] = {
79 DRM_FORMAT_C8,
80 DRM_FORMAT_RGB565,
81 DRM_FORMAT_XRGB8888,
82 DRM_FORMAT_XBGR8888,
83 DRM_FORMAT_ARGB8888,
84 DRM_FORMAT_ABGR8888,
85 DRM_FORMAT_XRGB2101010,
86 DRM_FORMAT_XBGR2101010,
87 DRM_FORMAT_YUYV,
88 DRM_FORMAT_YVYU,
89 DRM_FORMAT_UYVY,
90 DRM_FORMAT_VYUY,
91};
92
93/* Cursor formats */
94static const uint32_t intel_cursor_formats[] = {
95 DRM_FORMAT_ARGB8888,
96};
97
98static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
99
100static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
101 struct intel_crtc_state *pipe_config);
102static void ironlake_pch_clock_get(struct intel_crtc *crtc,
103 struct intel_crtc_state *pipe_config);
104
105static int intel_framebuffer_init(struct drm_device *dev,
106 struct intel_framebuffer *ifb,
107 struct drm_mode_fb_cmd2 *mode_cmd,
108 struct drm_i915_gem_object *obj);
109static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
110static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
111static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
112 struct intel_link_m_n *m_n,
113 struct intel_link_m_n *m2_n2);
114static void ironlake_set_pipeconf(struct drm_crtc *crtc);
115static void haswell_set_pipeconf(struct drm_crtc *crtc);
116static void intel_set_pipe_csc(struct drm_crtc *crtc);
117static void vlv_prepare_pll(struct intel_crtc *crtc,
118 const struct intel_crtc_state *pipe_config);
119static void chv_prepare_pll(struct intel_crtc *crtc,
120 const struct intel_crtc_state *pipe_config);
121static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
122static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
123static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
124 struct intel_crtc_state *crtc_state);
125static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
126 int num_connectors);
127static void skylake_pfit_enable(struct intel_crtc *crtc);
128static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
129static void ironlake_pfit_enable(struct intel_crtc *crtc);
130static void intel_modeset_setup_hw_state(struct drm_device *dev);
131static void intel_pre_disable_primary(struct drm_crtc *crtc);
132
133typedef struct {
134 int min, max;
135} intel_range_t;
136
137typedef struct {
138 int dot_limit;
139 int p2_slow, p2_fast;
140} intel_p2_t;
141
142typedef struct intel_limit intel_limit_t;
143struct intel_limit {
144 intel_range_t dot, vco, n, m, m1, m2, p, p1;
145 intel_p2_t p2;
146};
147
148/* returns HPLL frequency in kHz */
149static int valleyview_get_vco(struct drm_i915_private *dev_priv)
150{
151 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
152
153 /* Obtain SKU information */
154 mutex_lock(&dev_priv->sb_lock);
155 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
156 CCK_FUSE_HPLL_FREQ_MASK;
157 mutex_unlock(&dev_priv->sb_lock);
158
159 return vco_freq[hpll_freq] * 1000;
160}
161
162static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
163 const char *name, u32 reg)
164{
165 u32 val;
166 int divider;
167
168 if (dev_priv->hpll_freq == 0)
169 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
170
171 mutex_lock(&dev_priv->sb_lock);
172 val = vlv_cck_read(dev_priv, reg);
173 mutex_unlock(&dev_priv->sb_lock);
174
175 divider = val & CCK_FREQUENCY_VALUES;
176
177 WARN((val & CCK_FREQUENCY_STATUS) !=
178 (divider << CCK_FREQUENCY_STATUS_SHIFT),
179 "%s change in progress\n", name);
180
181 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
182}
183
184int
185intel_pch_rawclk(struct drm_device *dev)
186{
187 struct drm_i915_private *dev_priv = dev->dev_private;
188
189 WARN_ON(!HAS_PCH_SPLIT(dev));
190
191 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
192}
193
194/* hrawclock is 1/4 the FSB frequency */
195int intel_hrawclk(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 uint32_t clkcfg;
199
200 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
201 if (IS_VALLEYVIEW(dev))
202 return 200;
203
204 clkcfg = I915_READ(CLKCFG);
205 switch (clkcfg & CLKCFG_FSB_MASK) {
206 case CLKCFG_FSB_400:
207 return 100;
208 case CLKCFG_FSB_533:
209 return 133;
210 case CLKCFG_FSB_667:
211 return 166;
212 case CLKCFG_FSB_800:
213 return 200;
214 case CLKCFG_FSB_1067:
215 return 266;
216 case CLKCFG_FSB_1333:
217 return 333;
218 /* these two are just a guess; one of them might be right */
219 case CLKCFG_FSB_1600:
220 case CLKCFG_FSB_1600_ALT:
221 return 400;
222 default:
223 return 133;
224 }
225}
226
227static void intel_update_czclk(struct drm_i915_private *dev_priv)
228{
229 if (!IS_VALLEYVIEW(dev_priv))
230 return;
231
232 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
233 CCK_CZ_CLOCK_CONTROL);
234
235 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
236}
237
238static inline u32 /* units of 100MHz */
239intel_fdi_link_freq(struct drm_device *dev)
240{
241 if (IS_GEN5(dev)) {
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
244 } else
245 return 27;
246}
247
248static const intel_limit_t intel_limits_i8xx_dac = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 2 },
259};
260
261static const intel_limit_t intel_limits_i8xx_dvo = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 2, .max = 33 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 4, .p2_fast = 4 },
272};
273
274static const intel_limit_t intel_limits_i8xx_lvds = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 908000, .max = 1512000 },
277 .n = { .min = 2, .max = 16 },
278 .m = { .min = 96, .max = 140 },
279 .m1 = { .min = 18, .max = 26 },
280 .m2 = { .min = 6, .max = 16 },
281 .p = { .min = 4, .max = 128 },
282 .p1 = { .min = 1, .max = 6 },
283 .p2 = { .dot_limit = 165000,
284 .p2_slow = 14, .p2_fast = 7 },
285};
286
287static const intel_limit_t intel_limits_i9xx_sdvo = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 5, .max = 80 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 200000,
297 .p2_slow = 10, .p2_fast = 5 },
298};
299
300static const intel_limit_t intel_limits_i9xx_lvds = {
301 .dot = { .min = 20000, .max = 400000 },
302 .vco = { .min = 1400000, .max = 2800000 },
303 .n = { .min = 1, .max = 6 },
304 .m = { .min = 70, .max = 120 },
305 .m1 = { .min = 8, .max = 18 },
306 .m2 = { .min = 3, .max = 7 },
307 .p = { .min = 7, .max = 98 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 112000,
310 .p2_slow = 14, .p2_fast = 7 },
311};
312
313
314static const intel_limit_t intel_limits_g4x_sdvo = {
315 .dot = { .min = 25000, .max = 270000 },
316 .vco = { .min = 1750000, .max = 3500000},
317 .n = { .min = 1, .max = 4 },
318 .m = { .min = 104, .max = 138 },
319 .m1 = { .min = 17, .max = 23 },
320 .m2 = { .min = 5, .max = 11 },
321 .p = { .min = 10, .max = 30 },
322 .p1 = { .min = 1, .max = 3},
323 .p2 = { .dot_limit = 270000,
324 .p2_slow = 10,
325 .p2_fast = 10
326 },
327};
328
329static const intel_limit_t intel_limits_g4x_hdmi = {
330 .dot = { .min = 22000, .max = 400000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 16, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 5, .max = 80 },
337 .p1 = { .min = 1, .max = 8},
338 .p2 = { .dot_limit = 165000,
339 .p2_slow = 10, .p2_fast = 5 },
340};
341
342static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
343 .dot = { .min = 20000, .max = 115000 },
344 .vco = { .min = 1750000, .max = 3500000 },
345 .n = { .min = 1, .max = 3 },
346 .m = { .min = 104, .max = 138 },
347 .m1 = { .min = 17, .max = 23 },
348 .m2 = { .min = 5, .max = 11 },
349 .p = { .min = 28, .max = 112 },
350 .p1 = { .min = 2, .max = 8 },
351 .p2 = { .dot_limit = 0,
352 .p2_slow = 14, .p2_fast = 14
353 },
354};
355
356static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
357 .dot = { .min = 80000, .max = 224000 },
358 .vco = { .min = 1750000, .max = 3500000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 104, .max = 138 },
361 .m1 = { .min = 17, .max = 23 },
362 .m2 = { .min = 5, .max = 11 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 0,
366 .p2_slow = 7, .p2_fast = 7
367 },
368};
369
370static const intel_limit_t intel_limits_pineview_sdvo = {
371 .dot = { .min = 20000, .max = 400000},
372 .vco = { .min = 1700000, .max = 3500000 },
373 /* Pineview's Ncounter is a ring counter */
374 .n = { .min = 3, .max = 6 },
375 .m = { .min = 2, .max = 256 },
376 /* Pineview only has one combined m divider, which we treat as m2. */
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 5, .max = 80 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 200000,
382 .p2_slow = 10, .p2_fast = 5 },
383};
384
385static const intel_limit_t intel_limits_pineview_lvds = {
386 .dot = { .min = 20000, .max = 400000 },
387 .vco = { .min = 1700000, .max = 3500000 },
388 .n = { .min = 3, .max = 6 },
389 .m = { .min = 2, .max = 256 },
390 .m1 = { .min = 0, .max = 0 },
391 .m2 = { .min = 0, .max = 254 },
392 .p = { .min = 7, .max = 112 },
393 .p1 = { .min = 1, .max = 8 },
394 .p2 = { .dot_limit = 112000,
395 .p2_slow = 14, .p2_fast = 14 },
396};
397
398/* Ironlake / Sandybridge
399 *
400 * We calculate clock using (register_value + 2) for N/M1/M2, so here
401 * the range value for them is (actual_value - 2).
402 */
403static const intel_limit_t intel_limits_ironlake_dac = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 5 },
407 .m = { .min = 79, .max = 127 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 5, .max = 80 },
411 .p1 = { .min = 1, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 10, .p2_fast = 5 },
414};
415
416static const intel_limit_t intel_limits_ironlake_single_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 118 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 28, .max = 112 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 14, .p2_fast = 14 },
427};
428
429static const intel_limit_t intel_limits_ironlake_dual_lvds = {
430 .dot = { .min = 25000, .max = 350000 },
431 .vco = { .min = 1760000, .max = 3510000 },
432 .n = { .min = 1, .max = 3 },
433 .m = { .min = 79, .max = 127 },
434 .m1 = { .min = 12, .max = 22 },
435 .m2 = { .min = 5, .max = 9 },
436 .p = { .min = 14, .max = 56 },
437 .p1 = { .min = 2, .max = 8 },
438 .p2 = { .dot_limit = 225000,
439 .p2_slow = 7, .p2_fast = 7 },
440};
441
442/* LVDS 100mhz refclk limits. */
443static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 2 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 28, .max = 112 },
451 .p1 = { .min = 2, .max = 8 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 14, .p2_fast = 14 },
454};
455
456static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
457 .dot = { .min = 25000, .max = 350000 },
458 .vco = { .min = 1760000, .max = 3510000 },
459 .n = { .min = 1, .max = 3 },
460 .m = { .min = 79, .max = 126 },
461 .m1 = { .min = 12, .max = 22 },
462 .m2 = { .min = 5, .max = 9 },
463 .p = { .min = 14, .max = 42 },
464 .p1 = { .min = 2, .max = 6 },
465 .p2 = { .dot_limit = 225000,
466 .p2_slow = 7, .p2_fast = 7 },
467};
468
469static const intel_limit_t intel_limits_vlv = {
470 /*
471 * These are the data rate limits (measured in fast clocks)
472 * since those are the strictest limits we have. The fast
473 * clock and actual rate limits are more relaxed, so checking
474 * them would make no difference.
475 */
476 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
477 .vco = { .min = 4000000, .max = 6000000 },
478 .n = { .min = 1, .max = 7 },
479 .m1 = { .min = 2, .max = 3 },
480 .m2 = { .min = 11, .max = 156 },
481 .p1 = { .min = 2, .max = 3 },
482 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
483};
484
485static const intel_limit_t intel_limits_chv = {
486 /*
487 * These are the data rate limits (measured in fast clocks)
488 * since those are the strictest limits we have. The fast
489 * clock and actual rate limits are more relaxed, so checking
490 * them would make no difference.
491 */
492 .dot = { .min = 25000 * 5, .max = 540000 * 5},
493 .vco = { .min = 4800000, .max = 6480000 },
494 .n = { .min = 1, .max = 1 },
495 .m1 = { .min = 2, .max = 2 },
496 .m2 = { .min = 24 << 22, .max = 175 << 22 },
497 .p1 = { .min = 2, .max = 4 },
498 .p2 = { .p2_slow = 1, .p2_fast = 14 },
499};
500
501static const intel_limit_t intel_limits_bxt = {
502 /* FIXME: find real dot limits */
503 .dot = { .min = 0, .max = INT_MAX },
504 .vco = { .min = 4800000, .max = 6700000 },
505 .n = { .min = 1, .max = 1 },
506 .m1 = { .min = 2, .max = 2 },
507 /* FIXME: find real m2 limits */
508 .m2 = { .min = 2 << 22, .max = 255 << 22 },
509 .p1 = { .min = 2, .max = 4 },
510 .p2 = { .p2_slow = 1, .p2_fast = 20 },
511};
512
513static bool
514needs_modeset(struct drm_crtc_state *state)
515{
516 return drm_atomic_crtc_needs_modeset(state);
517}
518
519/**
520 * Returns whether any output on the specified pipe is of the specified type
521 */
522bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
523{
524 struct drm_device *dev = crtc->base.dev;
525 struct intel_encoder *encoder;
526
527 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
528 if (encoder->type == type)
529 return true;
530
531 return false;
532}
533
534/**
535 * Returns whether any output on the specified pipe will have the specified
536 * type after a staged modeset is complete, i.e., the same as
537 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
538 * encoder->crtc.
539 */
540static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
541 int type)
542{
543 struct drm_atomic_state *state = crtc_state->base.state;
544 struct drm_connector *connector;
545 struct drm_connector_state *connector_state;
546 struct intel_encoder *encoder;
547 int i, num_connectors = 0;
548
549 for_each_connector_in_state(state, connector, connector_state, i) {
550 if (connector_state->crtc != crtc_state->base.crtc)
551 continue;
552
553 num_connectors++;
554
555 encoder = to_intel_encoder(connector_state->best_encoder);
556 if (encoder->type == type)
557 return true;
558 }
559
560 WARN_ON(num_connectors == 0);
561
562 return false;
563}
564
565static const intel_limit_t *
566intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
567{
568 struct drm_device *dev = crtc_state->base.crtc->dev;
569 const intel_limit_t *limit;
570
571 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
572 if (intel_is_dual_link_lvds(dev)) {
573 if (refclk == 100000)
574 limit = &intel_limits_ironlake_dual_lvds_100m;
575 else
576 limit = &intel_limits_ironlake_dual_lvds;
577 } else {
578 if (refclk == 100000)
579 limit = &intel_limits_ironlake_single_lvds_100m;
580 else
581 limit = &intel_limits_ironlake_single_lvds;
582 }
583 } else
584 limit = &intel_limits_ironlake_dac;
585
586 return limit;
587}
588
589static const intel_limit_t *
590intel_g4x_limit(struct intel_crtc_state *crtc_state)
591{
592 struct drm_device *dev = crtc_state->base.crtc->dev;
593 const intel_limit_t *limit;
594
595 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
596 if (intel_is_dual_link_lvds(dev))
597 limit = &intel_limits_g4x_dual_channel_lvds;
598 else
599 limit = &intel_limits_g4x_single_channel_lvds;
600 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
601 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
602 limit = &intel_limits_g4x_hdmi;
603 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
604 limit = &intel_limits_g4x_sdvo;
605 } else /* The option is for other outputs */
606 limit = &intel_limits_i9xx_sdvo;
607
608 return limit;
609}
610
611static const intel_limit_t *
612intel_limit(struct intel_crtc_state *crtc_state, int refclk)
613{
614 struct drm_device *dev = crtc_state->base.crtc->dev;
615 const intel_limit_t *limit;
616
617 if (IS_BROXTON(dev))
618 limit = &intel_limits_bxt;
619 else if (HAS_PCH_SPLIT(dev))
620 limit = intel_ironlake_limit(crtc_state, refclk);
621 else if (IS_G4X(dev)) {
622 limit = intel_g4x_limit(crtc_state);
623 } else if (IS_PINEVIEW(dev)) {
624 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
625 limit = &intel_limits_pineview_lvds;
626 else
627 limit = &intel_limits_pineview_sdvo;
628 } else if (IS_CHERRYVIEW(dev)) {
629 limit = &intel_limits_chv;
630 } else if (IS_VALLEYVIEW(dev)) {
631 limit = &intel_limits_vlv;
632 } else if (!IS_GEN2(dev)) {
633 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
634 limit = &intel_limits_i9xx_lvds;
635 else
636 limit = &intel_limits_i9xx_sdvo;
637 } else {
638 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
639 limit = &intel_limits_i8xx_lvds;
640 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
641 limit = &intel_limits_i8xx_dvo;
642 else
643 limit = &intel_limits_i8xx_dac;
644 }
645 return limit;
646}
647
648/*
649 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
650 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
651 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
652 * The helpers' return value is the rate of the clock that is fed to the
653 * display engine's pipe which can be the above fast dot clock rate or a
654 * divided-down version of it.
655 */
656/* m1 is reserved as 0 in Pineview, n is a ring counter */
657static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
658{
659 clock->m = clock->m2 + 2;
660 clock->p = clock->p1 * clock->p2;
661 if (WARN_ON(clock->n == 0 || clock->p == 0))
662 return 0;
663 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
664 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
665
666 return clock->dot;
667}
668
669static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
670{
671 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
672}
673
674static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
675{
676 clock->m = i9xx_dpll_compute_m(clock);
677 clock->p = clock->p1 * clock->p2;
678 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
679 return 0;
680 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
681 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682
683 return clock->dot;
684}
685
686static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
687{
688 clock->m = clock->m1 * clock->m2;
689 clock->p = clock->p1 * clock->p2;
690 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 return 0;
692 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696}
697
698int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
699{
700 clock->m = clock->m1 * clock->m2;
701 clock->p = clock->p1 * clock->p2;
702 if (WARN_ON(clock->n == 0 || clock->p == 0))
703 return 0;
704 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
705 clock->n << 22);
706 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
707
708 return clock->dot / 5;
709}
710
711#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
712/**
713 * Returns whether the given set of divisors are valid for a given refclk with
714 * the given connectors.
715 */
716
717static bool intel_PLL_is_valid(struct drm_device *dev,
718 const intel_limit_t *limit,
719 const intel_clock_t *clock)
720{
721 if (clock->n < limit->n.min || limit->n.max < clock->n)
722 INTELPllInvalid("n out of range\n");
723 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
724 INTELPllInvalid("p1 out of range\n");
725 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
726 INTELPllInvalid("m2 out of range\n");
727 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
728 INTELPllInvalid("m1 out of range\n");
729
730 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
731 if (clock->m1 <= clock->m2)
732 INTELPllInvalid("m1 <= m2\n");
733
734 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
735 if (clock->p < limit->p.min || limit->p.max < clock->p)
736 INTELPllInvalid("p out of range\n");
737 if (clock->m < limit->m.min || limit->m.max < clock->m)
738 INTELPllInvalid("m out of range\n");
739 }
740
741 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
742 INTELPllInvalid("vco out of range\n");
743 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
744 * connector, etc., rather than just a single range.
745 */
746 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
747 INTELPllInvalid("dot out of range\n");
748
749 return true;
750}
751
752static int
753i9xx_select_p2_div(const intel_limit_t *limit,
754 const struct intel_crtc_state *crtc_state,
755 int target)
756{
757 struct drm_device *dev = crtc_state->base.crtc->dev;
758
759 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
760 /*
761 * For LVDS just rely on its current settings for dual-channel.
762 * We haven't figured out how to reliably set up different
763 * single/dual channel state, if we even can.
764 */
765 if (intel_is_dual_link_lvds(dev))
766 return limit->p2.p2_fast;
767 else
768 return limit->p2.p2_slow;
769 } else {
770 if (target < limit->p2.dot_limit)
771 return limit->p2.p2_slow;
772 else
773 return limit->p2.p2_fast;
774 }
775}
776
777static bool
778i9xx_find_best_dpll(const intel_limit_t *limit,
779 struct intel_crtc_state *crtc_state,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782{
783 struct drm_device *dev = crtc_state->base.crtc->dev;
784 intel_clock_t clock;
785 int err = target;
786
787 memset(best_clock, 0, sizeof(*best_clock));
788
789 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
790
791 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
792 clock.m1++) {
793 for (clock.m2 = limit->m2.min;
794 clock.m2 <= limit->m2.max; clock.m2++) {
795 if (clock.m2 >= clock.m1)
796 break;
797 for (clock.n = limit->n.min;
798 clock.n <= limit->n.max; clock.n++) {
799 for (clock.p1 = limit->p1.min;
800 clock.p1 <= limit->p1.max; clock.p1++) {
801 int this_err;
802
803 i9xx_calc_dpll_params(refclk, &clock);
804 if (!intel_PLL_is_valid(dev, limit,
805 &clock))
806 continue;
807 if (match_clock &&
808 clock.p != match_clock->p)
809 continue;
810
811 this_err = abs(clock.dot - target);
812 if (this_err < err) {
813 *best_clock = clock;
814 err = this_err;
815 }
816 }
817 }
818 }
819 }
820
821 return (err != target);
822}
823
824static bool
825pnv_find_best_dpll(const intel_limit_t *limit,
826 struct intel_crtc_state *crtc_state,
827 int target, int refclk, intel_clock_t *match_clock,
828 intel_clock_t *best_clock)
829{
830 struct drm_device *dev = crtc_state->base.crtc->dev;
831 intel_clock_t clock;
832 int err = target;
833
834 memset(best_clock, 0, sizeof(*best_clock));
835
836 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
837
838 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
839 clock.m1++) {
840 for (clock.m2 = limit->m2.min;
841 clock.m2 <= limit->m2.max; clock.m2++) {
842 for (clock.n = limit->n.min;
843 clock.n <= limit->n.max; clock.n++) {
844 for (clock.p1 = limit->p1.min;
845 clock.p1 <= limit->p1.max; clock.p1++) {
846 int this_err;
847
848 pnv_calc_dpll_params(refclk, &clock);
849 if (!intel_PLL_is_valid(dev, limit,
850 &clock))
851 continue;
852 if (match_clock &&
853 clock.p != match_clock->p)
854 continue;
855
856 this_err = abs(clock.dot - target);
857 if (this_err < err) {
858 *best_clock = clock;
859 err = this_err;
860 }
861 }
862 }
863 }
864 }
865
866 return (err != target);
867}
868
869static bool
870g4x_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
874{
875 struct drm_device *dev = crtc_state->base.crtc->dev;
876 intel_clock_t clock;
877 int max_n;
878 bool found = false;
879 /* approximately equals target * 0.00585 */
880 int err_most = (target >> 8) + (target >> 9);
881
882 memset(best_clock, 0, sizeof(*best_clock));
883
884 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
885
886 max_n = limit->n.max;
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
889 /* based on hardware requirement, prefere larger m1,m2 */
890 for (clock.m1 = limit->m1.max;
891 clock.m1 >= limit->m1.min; clock.m1--) {
892 for (clock.m2 = limit->m2.max;
893 clock.m2 >= limit->m2.min; clock.m2--) {
894 for (clock.p1 = limit->p1.max;
895 clock.p1 >= limit->p1.min; clock.p1--) {
896 int this_err;
897
898 i9xx_calc_dpll_params(refclk, &clock);
899 if (!intel_PLL_is_valid(dev, limit,
900 &clock))
901 continue;
902
903 this_err = abs(clock.dot - target);
904 if (this_err < err_most) {
905 *best_clock = clock;
906 err_most = this_err;
907 max_n = clock.n;
908 found = true;
909 }
910 }
911 }
912 }
913 }
914 return found;
915}
916
917/*
918 * Check if the calculated PLL configuration is more optimal compared to the
919 * best configuration and error found so far. Return the calculated error.
920 */
921static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
922 const intel_clock_t *calculated_clock,
923 const intel_clock_t *best_clock,
924 unsigned int best_error_ppm,
925 unsigned int *error_ppm)
926{
927 /*
928 * For CHV ignore the error and consider only the P value.
929 * Prefer a bigger P value based on HW requirements.
930 */
931 if (IS_CHERRYVIEW(dev)) {
932 *error_ppm = 0;
933
934 return calculated_clock->p > best_clock->p;
935 }
936
937 if (WARN_ON_ONCE(!target_freq))
938 return false;
939
940 *error_ppm = div_u64(1000000ULL *
941 abs(target_freq - calculated_clock->dot),
942 target_freq);
943 /*
944 * Prefer a better P value over a better (smaller) error if the error
945 * is small. Ensure this preference for future configurations too by
946 * setting the error to 0.
947 */
948 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
949 *error_ppm = 0;
950
951 return true;
952 }
953
954 return *error_ppm + 10 < best_error_ppm;
955}
956
957static bool
958vlv_find_best_dpll(const intel_limit_t *limit,
959 struct intel_crtc_state *crtc_state,
960 int target, int refclk, intel_clock_t *match_clock,
961 intel_clock_t *best_clock)
962{
963 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
964 struct drm_device *dev = crtc->base.dev;
965 intel_clock_t clock;
966 unsigned int bestppm = 1000000;
967 /* min update 19.2 MHz */
968 int max_n = min(limit->n.max, refclk / 19200);
969 bool found = false;
970
971 target *= 5; /* fast clock */
972
973 memset(best_clock, 0, sizeof(*best_clock));
974
975 /* based on hardware requirement, prefer smaller n to precision */
976 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
977 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
978 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
979 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
980 clock.p = clock.p1 * clock.p2;
981 /* based on hardware requirement, prefer bigger m1,m2 values */
982 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
983 unsigned int ppm;
984
985 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
986 refclk * clock.m1);
987
988 vlv_calc_dpll_params(refclk, &clock);
989
990 if (!intel_PLL_is_valid(dev, limit,
991 &clock))
992 continue;
993
994 if (!vlv_PLL_is_optimal(dev, target,
995 &clock,
996 best_clock,
997 bestppm, &ppm))
998 continue;
999
1000 *best_clock = clock;
1001 bestppm = ppm;
1002 found = true;
1003 }
1004 }
1005 }
1006 }
1007
1008 return found;
1009}
1010
1011static bool
1012chv_find_best_dpll(const intel_limit_t *limit,
1013 struct intel_crtc_state *crtc_state,
1014 int target, int refclk, intel_clock_t *match_clock,
1015 intel_clock_t *best_clock)
1016{
1017 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1018 struct drm_device *dev = crtc->base.dev;
1019 unsigned int best_error_ppm;
1020 intel_clock_t clock;
1021 uint64_t m2;
1022 int found = false;
1023
1024 memset(best_clock, 0, sizeof(*best_clock));
1025 best_error_ppm = 1000000;
1026
1027 /*
1028 * Based on hardware doc, the n always set to 1, and m1 always
1029 * set to 2. If requires to support 200Mhz refclk, we need to
1030 * revisit this because n may not 1 anymore.
1031 */
1032 clock.n = 1, clock.m1 = 2;
1033 target *= 5; /* fast clock */
1034
1035 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1036 for (clock.p2 = limit->p2.p2_fast;
1037 clock.p2 >= limit->p2.p2_slow;
1038 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1039 unsigned int error_ppm;
1040
1041 clock.p = clock.p1 * clock.p2;
1042
1043 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1044 clock.n) << 22, refclk * clock.m1);
1045
1046 if (m2 > INT_MAX/clock.m1)
1047 continue;
1048
1049 clock.m2 = m2;
1050
1051 chv_calc_dpll_params(refclk, &clock);
1052
1053 if (!intel_PLL_is_valid(dev, limit, &clock))
1054 continue;
1055
1056 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1057 best_error_ppm, &error_ppm))
1058 continue;
1059
1060 *best_clock = clock;
1061 best_error_ppm = error_ppm;
1062 found = true;
1063 }
1064 }
1065
1066 return found;
1067}
1068
1069bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1070 intel_clock_t *best_clock)
1071{
1072 int refclk = i9xx_get_refclk(crtc_state, 0);
1073
1074 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1075 target_clock, refclk, NULL, best_clock);
1076}
1077
1078bool intel_crtc_active(struct drm_crtc *crtc)
1079{
1080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1081
1082 /* Be paranoid as we can arrive here with only partial
1083 * state retrieved from the hardware during setup.
1084 *
1085 * We can ditch the adjusted_mode.crtc_clock check as soon
1086 * as Haswell has gained clock readout/fastboot support.
1087 *
1088 * We can ditch the crtc->primary->fb check as soon as we can
1089 * properly reconstruct framebuffers.
1090 *
1091 * FIXME: The intel_crtc->active here should be switched to
1092 * crtc->state->active once we have proper CRTC states wired up
1093 * for atomic.
1094 */
1095 return intel_crtc->active && crtc->primary->state->fb &&
1096 intel_crtc->config->base.adjusted_mode.crtc_clock;
1097}
1098
1099enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1100 enum i915_pipe pipe)
1101{
1102 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1104
1105 return intel_crtc->config->cpu_transcoder;
1106}
1107
1108static bool pipe_dsl_stopped(struct drm_device *dev, enum i915_pipe pipe)
1109{
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 u32 reg = PIPEDSL(pipe);
1112 u32 line1, line2;
1113 u32 line_mask;
1114
1115 if (IS_GEN2(dev))
1116 line_mask = DSL_LINEMASK_GEN2;
1117 else
1118 line_mask = DSL_LINEMASK_GEN3;
1119
1120 line1 = I915_READ(reg) & line_mask;
1121 msleep(5);
1122 line2 = I915_READ(reg) & line_mask;
1123
1124 return line1 == line2;
1125}
1126
1127/*
1128 * intel_wait_for_pipe_off - wait for pipe to turn off
1129 * @crtc: crtc whose pipe to wait for
1130 *
1131 * After disabling a pipe, we can't wait for vblank in the usual way,
1132 * spinning on the vblank interrupt status bit, since we won't actually
1133 * see an interrupt when the pipe is disabled.
1134 *
1135 * On Gen4 and above:
1136 * wait for the pipe register state bit to turn off
1137 *
1138 * Otherwise:
1139 * wait for the display line value to settle (it usually
1140 * ends up stopping at the start of the next frame).
1141 *
1142 */
1143static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1144{
1145 struct drm_device *dev = crtc->base.dev;
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1148 enum i915_pipe pipe = crtc->pipe;
1149
1150 if (INTEL_INFO(dev)->gen >= 4) {
1151 int reg = PIPECONF(cpu_transcoder);
1152
1153 /* Wait for the Pipe State to go off */
1154 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1155 100))
1156 WARN(1, "pipe_off wait timed out\n");
1157 } else {
1158 /* Wait for the display line to settle */
1159 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1160 WARN(1, "pipe_off wait timed out\n");
1161 }
1162}
1163
1164static const char *state_string(bool enabled)
1165{
1166 return enabled ? "on" : "off";
1167}
1168
1169/* Only for pre-ILK configs */
1170void assert_pll(struct drm_i915_private *dev_priv,
1171 enum i915_pipe pipe, bool state)
1172{
1173 u32 val;
1174 bool cur_state;
1175
1176 val = I915_READ(DPLL(pipe));
1177 cur_state = !!(val & DPLL_VCO_ENABLE);
1178 I915_STATE_WARN(cur_state != state,
1179 "PLL state assertion failure (expected %s, current %s)\n",
1180 state_string(state), state_string(cur_state));
1181}
1182
1183/* XXX: the dsi pll is shared between MIPI DSI ports */
1184static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1185{
1186 u32 val;
1187 bool cur_state;
1188
1189 mutex_lock(&dev_priv->sb_lock);
1190 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1191 mutex_unlock(&dev_priv->sb_lock);
1192
1193 cur_state = val & DSI_PLL_VCO_EN;
1194 I915_STATE_WARN(cur_state != state,
1195 "DSI PLL state assertion failure (expected %s, current %s)\n",
1196 state_string(state), state_string(cur_state));
1197}
1198#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1199#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1200
1201struct intel_shared_dpll *
1202intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1203{
1204 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1205
1206 if (crtc->config->shared_dpll < 0)
1207 return NULL;
1208
1209 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1210}
1211
1212/* For ILK+ */
1213void assert_shared_dpll(struct drm_i915_private *dev_priv,
1214 struct intel_shared_dpll *pll,
1215 bool state)
1216{
1217 bool cur_state;
1218 struct intel_dpll_hw_state hw_state;
1219
1220 if (WARN (!pll,
1221 "asserting DPLL %s with no DPLL\n", state_string(state)))
1222 return;
1223
1224 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1225 I915_STATE_WARN(cur_state != state,
1226 "%s assertion failure (expected %s, current %s)\n",
1227 pll->name, state_string(state), state_string(cur_state));
1228}
1229
1230static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1231 enum i915_pipe pipe, bool state)
1232{
1233 bool cur_state;
1234 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1235 pipe);
1236
1237 if (HAS_DDI(dev_priv->dev)) {
1238 /* DDI does not have a specific FDI_TX register */
1239 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1240 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1241 } else {
1242 u32 val = I915_READ(FDI_TX_CTL(pipe));
1243 cur_state = !!(val & FDI_TX_ENABLE);
1244 }
1245 I915_STATE_WARN(cur_state != state,
1246 "FDI TX state assertion failure (expected %s, current %s)\n",
1247 state_string(state), state_string(cur_state));
1248}
1249#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1250#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1251
1252static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1253 enum i915_pipe pipe, bool state)
1254{
1255 u32 val;
1256 bool cur_state;
1257
1258 val = I915_READ(FDI_RX_CTL(pipe));
1259 cur_state = !!(val & FDI_RX_ENABLE);
1260 I915_STATE_WARN(cur_state != state,
1261 "FDI RX state assertion failure (expected %s, current %s)\n",
1262 state_string(state), state_string(cur_state));
1263}
1264#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1265#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1266
1267static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1268 enum i915_pipe pipe)
1269{
1270 u32 val;
1271
1272 /* ILK FDI PLL is always enabled */
1273 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1274 return;
1275
1276 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1277 if (HAS_DDI(dev_priv->dev))
1278 return;
1279
1280 val = I915_READ(FDI_TX_CTL(pipe));
1281 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1282}
1283
1284void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1285 enum i915_pipe pipe, bool state)
1286{
1287 u32 val;
1288 bool cur_state;
1289
1290 val = I915_READ(FDI_RX_CTL(pipe));
1291 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1292 I915_STATE_WARN(cur_state != state,
1293 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1294 state_string(state), state_string(cur_state));
1295}
1296
1297void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1298 enum i915_pipe pipe)
1299{
1300 struct drm_device *dev = dev_priv->dev;
1301 int pp_reg;
1302 u32 val;
1303 enum i915_pipe panel_pipe = PIPE_A;
1304 bool locked = true;
1305
1306 if (WARN_ON(HAS_DDI(dev)))
1307 return;
1308
1309 if (HAS_PCH_SPLIT(dev)) {
1310 u32 port_sel;
1311
1312 pp_reg = PCH_PP_CONTROL;
1313 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1314
1315 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1316 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1317 panel_pipe = PIPE_B;
1318 /* XXX: else fix for eDP */
1319 } else if (IS_VALLEYVIEW(dev)) {
1320 /* presumably write lock depends on pipe, not port select */
1321 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1322 panel_pipe = pipe;
1323 } else {
1324 pp_reg = PP_CONTROL;
1325 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1326 panel_pipe = PIPE_B;
1327 }
1328
1329 val = I915_READ(pp_reg);
1330 if (!(val & PANEL_POWER_ON) ||
1331 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1332 locked = false;
1333
1334 I915_STATE_WARN(panel_pipe == pipe && locked,
1335 "panel assertion failure, pipe %c regs locked\n",
1336 pipe_name(pipe));
1337}
1338
1339static void assert_cursor(struct drm_i915_private *dev_priv,
1340 enum i915_pipe pipe, bool state)
1341{
1342 struct drm_device *dev = dev_priv->dev;
1343 bool cur_state;
1344
1345 if (IS_845G(dev) || IS_I865G(dev))
1346 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1347 else
1348 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1349
1350 I915_STATE_WARN(cur_state != state,
1351 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1352 pipe_name(pipe), state_string(state), state_string(cur_state));
1353}
1354#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1355#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1356
1357void assert_pipe(struct drm_i915_private *dev_priv,
1358 enum i915_pipe pipe, bool state)
1359{
1360 bool cur_state;
1361 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1362 pipe);
1363
1364 /* if we need the pipe quirk it must be always on */
1365 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1366 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1367 state = true;
1368
1369 if (!intel_display_power_is_enabled(dev_priv,
1370 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1371 cur_state = false;
1372 } else {
1373 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1374 cur_state = !!(val & PIPECONF_ENABLE);
1375 }
1376
1377 I915_STATE_WARN(cur_state != state,
1378 "pipe %c assertion failure (expected %s, current %s)\n",
1379 pipe_name(pipe), state_string(state), state_string(cur_state));
1380}
1381
1382static void assert_plane(struct drm_i915_private *dev_priv,
1383 enum plane plane, bool state)
1384{
1385 u32 val;
1386 bool cur_state;
1387
1388 val = I915_READ(DSPCNTR(plane));
1389 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1390 I915_STATE_WARN(cur_state != state,
1391 "plane %c assertion failure (expected %s, current %s)\n",
1392 plane_name(plane), state_string(state), state_string(cur_state));
1393}
1394
1395#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1396#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1397
1398static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1399 enum i915_pipe pipe)
1400{
1401 struct drm_device *dev = dev_priv->dev;
1402 int i;
1403
1404 /* Primary planes are fixed to pipes on gen4+ */
1405 if (INTEL_INFO(dev)->gen >= 4) {
1406 u32 val = I915_READ(DSPCNTR(pipe));
1407 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1408 "plane %c assertion failure, should be disabled but not\n",
1409 plane_name(pipe));
1410 return;
1411 }
1412
1413 /* Need to check both planes against the pipe */
1414 for_each_pipe(dev_priv, i) {
1415 u32 val = I915_READ(DSPCNTR(i));
1416 enum i915_pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1417 DISPPLANE_SEL_PIPE_SHIFT;
1418 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1419 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(i), pipe_name(pipe));
1421 }
1422}
1423
1424static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1425 enum i915_pipe pipe)
1426{
1427 struct drm_device *dev = dev_priv->dev;
1428 int sprite;
1429
1430 if (INTEL_INFO(dev)->gen >= 9) {
1431 for_each_sprite(dev_priv, pipe, sprite) {
1432 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1433 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1434 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1435 sprite, pipe_name(pipe));
1436 }
1437 } else if (IS_VALLEYVIEW(dev)) {
1438 for_each_sprite(dev_priv, pipe, sprite) {
1439 u32 val = I915_READ(SPCNTR(pipe, sprite));
1440 I915_STATE_WARN(val & SP_ENABLE,
1441 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442 sprite_name(pipe, sprite), pipe_name(pipe));
1443 }
1444 } else if (INTEL_INFO(dev)->gen >= 7) {
1445 u32 val = I915_READ(SPRCTL(pipe));
1446 I915_STATE_WARN(val & SPRITE_ENABLE,
1447 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1448 plane_name(pipe), pipe_name(pipe));
1449 } else if (INTEL_INFO(dev)->gen >= 5) {
1450 u32 val = I915_READ(DVSCNTR(pipe));
1451 I915_STATE_WARN(val & DVS_ENABLE,
1452 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1453 plane_name(pipe), pipe_name(pipe));
1454 }
1455}
1456
1457static void assert_vblank_disabled(struct drm_crtc *crtc)
1458{
1459 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1460 drm_crtc_vblank_put(crtc);
1461}
1462
1463static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1464{
1465 u32 val;
1466 bool enabled;
1467
1468 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1469
1470 val = I915_READ(PCH_DREF_CONTROL);
1471 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1472 DREF_SUPERSPREAD_SOURCE_MASK));
1473 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1474}
1475
1476static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1477 enum i915_pipe pipe)
1478{
1479 u32 val;
1480 bool enabled;
1481
1482 val = I915_READ(PCH_TRANSCONF(pipe));
1483 enabled = !!(val & TRANS_ENABLE);
1484 I915_STATE_WARN(enabled,
1485 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1486 pipe_name(pipe));
1487}
1488
1489static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum i915_pipe pipe, u32 port_sel, u32 val)
1491{
1492 if ((val & DP_PORT_EN) == 0)
1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
1496 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1497 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1498 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1499 return false;
1500 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1501 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1502 return false;
1503 } else {
1504 if ((val & DP_PIPE_MASK) != (pipe << 30))
1505 return false;
1506 }
1507 return true;
1508}
1509
1510static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1511 enum i915_pipe pipe, u32 val)
1512{
1513 if ((val & SDVO_ENABLE) == 0)
1514 return false;
1515
1516 if (HAS_PCH_CPT(dev_priv->dev)) {
1517 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1518 return false;
1519 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1520 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1521 return false;
1522 } else {
1523 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1524 return false;
1525 }
1526 return true;
1527}
1528
1529static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum i915_pipe pipe, u32 val)
1531{
1532 if ((val & LVDS_PORT_EN) == 0)
1533 return false;
1534
1535 if (HAS_PCH_CPT(dev_priv->dev)) {
1536 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1537 return false;
1538 } else {
1539 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1540 return false;
1541 }
1542 return true;
1543}
1544
1545static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1546 enum i915_pipe pipe, u32 val)
1547{
1548 if ((val & ADPA_DAC_ENABLE) == 0)
1549 return false;
1550 if (HAS_PCH_CPT(dev_priv->dev)) {
1551 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1552 return false;
1553 } else {
1554 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1555 return false;
1556 }
1557 return true;
1558}
1559
1560static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1561 enum i915_pipe pipe, int reg, u32 port_sel)
1562{
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1565 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 reg, pipe_name(pipe));
1567
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1569 && (val & DP_PIPEB_SELECT),
1570 "IBX PCH dp port still using transcoder B\n");
1571}
1572
1573static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1574 enum i915_pipe pipe, int reg)
1575{
1576 u32 val = I915_READ(reg);
1577 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1578 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1579 reg, pipe_name(pipe));
1580
1581 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1582 && (val & SDVO_PIPE_B_SELECT),
1583 "IBX PCH hdmi port still using transcoder B\n");
1584}
1585
1586static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1587 enum i915_pipe pipe)
1588{
1589 u32 val;
1590
1591 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1592 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1593 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1594
1595 val = I915_READ(PCH_ADPA);
1596 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1597 "PCH VGA enabled on transcoder %c, should be disabled\n",
1598 pipe_name(pipe));
1599
1600 val = I915_READ(PCH_LVDS);
1601 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1602 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1603 pipe_name(pipe));
1604
1605 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1606 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1607 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1608}
1609
1610static void vlv_enable_pll(struct intel_crtc *crtc,
1611 const struct intel_crtc_state *pipe_config)
1612{
1613 struct drm_device *dev = crtc->base.dev;
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 int reg = DPLL(crtc->pipe);
1616 u32 dpll = pipe_config->dpll_hw_state.dpll;
1617
1618 assert_pipe_disabled(dev_priv, crtc->pipe);
1619
1620 /* No really, not for ILK+ */
1621 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1622
1623 /* PLL is protected by panel, make sure we can write it */
1624 if (IS_MOBILE(dev_priv->dev))
1625 assert_panel_unlocked(dev_priv, crtc->pipe);
1626
1627 I915_WRITE(reg, dpll);
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1632 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1633
1634 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1635 POSTING_READ(DPLL_MD(crtc->pipe));
1636
1637 /* We do this three times for luck */
1638 I915_WRITE(reg, dpll);
1639 POSTING_READ(reg);
1640 udelay(150); /* wait for warmup */
1641 I915_WRITE(reg, dpll);
1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647}
1648
1649static void chv_enable_pll(struct intel_crtc *crtc,
1650 const struct intel_crtc_state *pipe_config)
1651{
1652 struct drm_device *dev = crtc->base.dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 int pipe = crtc->pipe;
1655 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1656 u32 tmp;
1657
1658 assert_pipe_disabled(dev_priv, crtc->pipe);
1659
1660 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1661
1662 mutex_lock(&dev_priv->sb_lock);
1663
1664 /* Enable back the 10bit clock to display controller */
1665 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1666 tmp |= DPIO_DCLKP_EN;
1667 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1668
1669 mutex_unlock(&dev_priv->sb_lock);
1670
1671 /*
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 */
1674 udelay(1);
1675
1676 /* Enable PLL */
1677 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1678
1679 /* Check PLL is locked */
1680 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1681 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
1683 /* not sure when this should be written */
1684 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1685 POSTING_READ(DPLL_MD(pipe));
1686}
1687
1688static int intel_num_dvo_pipes(struct drm_device *dev)
1689{
1690 struct intel_crtc *crtc;
1691 int count = 0;
1692
1693 for_each_intel_crtc(dev, crtc)
1694 count += crtc->base.state->active &&
1695 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1696
1697 return count;
1698}
1699
1700static void i9xx_enable_pll(struct intel_crtc *crtc)
1701{
1702 struct drm_device *dev = crtc->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 int reg = DPLL(crtc->pipe);
1705 u32 dpll = crtc->config->dpll_hw_state.dpll;
1706
1707 assert_pipe_disabled(dev_priv, crtc->pipe);
1708
1709 /* No really, not for ILK+ */
1710 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1711
1712 /* PLL is protected by panel, make sure we can write it */
1713 if (IS_MOBILE(dev) && !IS_I830(dev))
1714 assert_panel_unlocked(dev_priv, crtc->pipe);
1715
1716 /* Enable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1718 /*
1719 * It appears to be important that we don't enable this
1720 * for the current pipe before otherwise configuring the
1721 * PLL. No idea how this should be handled if multiple
1722 * DVO outputs are enabled simultaneosly.
1723 */
1724 dpll |= DPLL_DVO_2X_MODE;
1725 I915_WRITE(DPLL(!crtc->pipe),
1726 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1727 }
1728
1729 /*
1730 * Apparently we need to have VGA mode enabled prior to changing
1731 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1732 * dividers, even though the register value does change.
1733 */
1734 I915_WRITE(reg, 0);
1735
1736 I915_WRITE(reg, dpll);
1737
1738 /* Wait for the clocks to stabilize. */
1739 POSTING_READ(reg);
1740 udelay(150);
1741
1742 if (INTEL_INFO(dev)->gen >= 4) {
1743 I915_WRITE(DPLL_MD(crtc->pipe),
1744 crtc->config->dpll_hw_state.dpll_md);
1745 } else {
1746 /* The pixel multiplier can only be updated once the
1747 * DPLL is enabled and the clocks are stable.
1748 *
1749 * So write it again.
1750 */
1751 I915_WRITE(reg, dpll);
1752 }
1753
1754 /* We do this three times for luck */
1755 I915_WRITE(reg, dpll);
1756 POSTING_READ(reg);
1757 udelay(150); /* wait for warmup */
1758 I915_WRITE(reg, dpll);
1759 POSTING_READ(reg);
1760 udelay(150); /* wait for warmup */
1761 I915_WRITE(reg, dpll);
1762 POSTING_READ(reg);
1763 udelay(150); /* wait for warmup */
1764}
1765
1766/**
1767 * i9xx_disable_pll - disable a PLL
1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe PLL to disable
1770 *
1771 * Disable the PLL for @pipe, making sure the pipe is off first.
1772 *
1773 * Note! This is for pre-ILK only.
1774 */
1775static void i9xx_disable_pll(struct intel_crtc *crtc)
1776{
1777 struct drm_device *dev = crtc->base.dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 enum i915_pipe pipe = crtc->pipe;
1780
1781 /* Disable DVO 2x clock on both PLLs if necessary */
1782 if (IS_I830(dev) &&
1783 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1784 !intel_num_dvo_pipes(dev)) {
1785 I915_WRITE(DPLL(PIPE_B),
1786 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1787 I915_WRITE(DPLL(PIPE_A),
1788 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1789 }
1790
1791 /* Don't disable pipe or pipe PLLs if needed */
1792 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1793 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1794 return;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
1799 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1800 POSTING_READ(DPLL(pipe));
1801}
1802
1803static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1804{
1805 u32 val;
1806
1807 /* Make sure the pipe isn't still relying on us */
1808 assert_pipe_disabled(dev_priv, pipe);
1809
1810 /*
1811 * Leave integrated clock source and reference clock enabled for pipe B.
1812 * The latter is needed for VGA hotplug / manual detection.
1813 */
1814 val = DPLL_VGA_MODE_DIS;
1815 if (pipe == PIPE_B)
1816 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1817 I915_WRITE(DPLL(pipe), val);
1818 POSTING_READ(DPLL(pipe));
1819
1820}
1821
1822static void chv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1823{
1824 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1825 u32 val;
1826
1827 /* Make sure the pipe isn't still relying on us */
1828 assert_pipe_disabled(dev_priv, pipe);
1829
1830 /* Set PLL en = 0 */
1831 val = DPLL_SSC_REF_CLK_CHV |
1832 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1833 if (pipe != PIPE_A)
1834 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1835 I915_WRITE(DPLL(pipe), val);
1836 POSTING_READ(DPLL(pipe));
1837
1838 mutex_lock(&dev_priv->sb_lock);
1839
1840 /* Disable 10bit clock to display controller */
1841 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1842 val &= ~DPIO_DCLKP_EN;
1843 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1844
1845 mutex_unlock(&dev_priv->sb_lock);
1846}
1847
1848void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1849 struct intel_digital_port *dport,
1850 unsigned int expected_mask)
1851{
1852 u32 port_mask;
1853 int dpll_reg;
1854
1855 switch (dport->port) {
1856 case PORT_B:
1857 port_mask = DPLL_PORTB_READY_MASK;
1858 dpll_reg = DPLL(0);
1859 break;
1860 case PORT_C:
1861 port_mask = DPLL_PORTC_READY_MASK;
1862 dpll_reg = DPLL(0);
1863 expected_mask <<= 4;
1864 break;
1865 case PORT_D:
1866 port_mask = DPLL_PORTD_READY_MASK;
1867 dpll_reg = DPIO_PHY_STATUS;
1868 break;
1869 default:
1870 BUG();
1871 }
1872
1873 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1874 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1875 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1876}
1877
1878static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1879{
1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1883
1884 if (WARN_ON(pll == NULL))
1885 return;
1886
1887 WARN_ON(!pll->config.crtc_mask);
1888 if (pll->active == 0) {
1889 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1890 WARN_ON(pll->on);
1891 assert_shared_dpll_disabled(dev_priv, pll);
1892
1893 pll->mode_set(dev_priv, pll);
1894 }
1895}
1896
1897/**
1898 * intel_enable_shared_dpll - enable PCH PLL
1899 * @dev_priv: i915 private structure
1900 * @pipe: pipe PLL to enable
1901 *
1902 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1903 * drives the transcoder clock.
1904 */
1905static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1906{
1907 struct drm_device *dev = crtc->base.dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
1909 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1910
1911 if (WARN_ON(pll == NULL))
1912 return;
1913
1914 if (WARN_ON(pll->config.crtc_mask == 0))
1915 return;
1916
1917 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1918 pll->name, pll->active, pll->on,
1919 crtc->base.base.id);
1920
1921 if (pll->active++) {
1922 WARN_ON(!pll->on);
1923 assert_shared_dpll_enabled(dev_priv, pll);
1924 return;
1925 }
1926 WARN_ON(pll->on);
1927
1928 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1929
1930 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1931 pll->enable(dev_priv, pll);
1932 pll->on = true;
1933}
1934
1935static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1936{
1937 struct drm_device *dev = crtc->base.dev;
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1940
1941 /* PCH only available on ILK+ */
1942 if (INTEL_INFO(dev)->gen < 5)
1943 return;
1944
1945 if (pll == NULL)
1946 return;
1947
1948 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1949 return;
1950
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
1953 crtc->base.base.id);
1954
1955 if (WARN_ON(pll->active == 0)) {
1956 assert_shared_dpll_disabled(dev_priv, pll);
1957 return;
1958 }
1959
1960 assert_shared_dpll_enabled(dev_priv, pll);
1961 WARN_ON(!pll->on);
1962 if (--pll->active)
1963 return;
1964
1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966 pll->disable(dev_priv, pll);
1967 pll->on = false;
1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1970}
1971
1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum i915_pipe pipe)
1974{
1975 struct drm_device *dev = dev_priv->dev;
1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 uint32_t reg, val, pipeconf_val;
1979
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev));
1982
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv,
1985 intel_crtc_to_shared_dpll(intel_crtc));
1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
1998 }
1999
2000 reg = PCH_TRANSCONF(pipe);
2001 val = I915_READ(reg);
2002 pipeconf_val = I915_READ(PIPECONF(pipe));
2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * Make the BPC in transcoder be consistent with
2007 * that in pipeconf reg. For HDMI we must use 8bpc
2008 * here for both 8bpc and 12bpc.
2009 */
2010 val &= ~PIPECONF_BPC_MASK;
2011 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2012 val |= PIPECONF_8BPC;
2013 else
2014 val |= pipeconf_val & PIPECONF_BPC_MASK;
2015 }
2016
2017 val &= ~TRANS_INTERLACE_MASK;
2018 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2019 if (HAS_PCH_IBX(dev_priv->dev) &&
2020 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2021 val |= TRANS_LEGACY_INTERLACED_ILK;
2022 else
2023 val |= TRANS_INTERLACED;
2024 else
2025 val |= TRANS_PROGRESSIVE;
2026
2027 I915_WRITE(reg, val | TRANS_ENABLE);
2028 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2029 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2030}
2031
2032static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2033 enum transcoder cpu_transcoder)
2034{
2035 u32 val, pipeconf_val;
2036
2037 /* PCH only available on ILK+ */
2038 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2039
2040 /* FDI must be feeding us bits for PCH ports */
2041 assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder);
2042 assert_fdi_rx_enabled(dev_priv, (enum i915_pipe) TRANSCODER_A);
2043
2044 /* Workaround: set timing override bit. */
2045 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2046 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2047 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2048
2049 val = TRANS_ENABLE;
2050 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2051
2052 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2053 PIPECONF_INTERLACED_ILK)
2054 val |= TRANS_INTERLACED;
2055 else
2056 val |= TRANS_PROGRESSIVE;
2057
2058 I915_WRITE(LPT_TRANSCONF, val);
2059 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2060 DRM_ERROR("Failed to enable PCH transcoder\n");
2061}
2062
2063static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2064 enum i915_pipe pipe)
2065{
2066 struct drm_device *dev = dev_priv->dev;
2067 uint32_t reg, val;
2068
2069 /* FDI relies on the transcoder */
2070 assert_fdi_tx_disabled(dev_priv, pipe);
2071 assert_fdi_rx_disabled(dev_priv, pipe);
2072
2073 /* Ports must be off as well */
2074 assert_pch_ports_disabled(dev_priv, pipe);
2075
2076 reg = PCH_TRANSCONF(pipe);
2077 val = I915_READ(reg);
2078 val &= ~TRANS_ENABLE;
2079 I915_WRITE(reg, val);
2080 /* wait for PCH transcoder off, transcoder state */
2081 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2082 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2083
2084 if (!HAS_PCH_IBX(dev)) {
2085 /* Workaround: Clear the timing override chicken bit again. */
2086 reg = TRANS_CHICKEN2(pipe);
2087 val = I915_READ(reg);
2088 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2089 I915_WRITE(reg, val);
2090 }
2091}
2092
2093static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2094{
2095 u32 val;
2096
2097 val = I915_READ(LPT_TRANSCONF);
2098 val &= ~TRANS_ENABLE;
2099 I915_WRITE(LPT_TRANSCONF, val);
2100 /* wait for PCH transcoder off, transcoder state */
2101 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2102 DRM_ERROR("Failed to disable PCH transcoder\n");
2103
2104 /* Workaround: clear timing override bit. */
2105 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2106 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2107 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2108}
2109
2110/**
2111 * intel_enable_pipe - enable a pipe, asserting requirements
2112 * @crtc: crtc responsible for the pipe
2113 *
2114 * Enable @crtc's pipe, making sure that various hardware specific requirements
2115 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2116 */
2117static void intel_enable_pipe(struct intel_crtc *crtc)
2118{
2119 struct drm_device *dev = crtc->base.dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 enum i915_pipe pipe = crtc->pipe;
2122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2123 pipe);
2124 enum i915_pipe pch_transcoder;
2125 int reg;
2126 u32 val;
2127
2128 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2129
2130 assert_planes_disabled(dev_priv, pipe);
2131 assert_cursor_disabled(dev_priv, pipe);
2132 assert_sprites_disabled(dev_priv, pipe);
2133
2134 if (HAS_PCH_LPT(dev_priv->dev))
2135 pch_transcoder = (enum i915_pipe)TRANSCODER_A;
2136 else
2137 pch_transcoder = pipe;
2138
2139 /*
2140 * A pipe without a PLL won't actually be able to drive bits from
2141 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2142 * need the check.
2143 */
2144 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2145 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2146 assert_dsi_pll_enabled(dev_priv);
2147 else
2148 assert_pll_enabled(dev_priv, pipe);
2149 else {
2150 if (crtc->config->has_pch_encoder) {
2151 /* if driving the PCH, we need FDI enabled */
2152 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2153 assert_fdi_tx_pll_enabled(dev_priv,
2154 (enum i915_pipe) cpu_transcoder);
2155 }
2156 /* FIXME: assert CPU port conditions for SNB+ */
2157 }
2158
2159 reg = PIPECONF(cpu_transcoder);
2160 val = I915_READ(reg);
2161 if (val & PIPECONF_ENABLE) {
2162 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2163 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2164 return;
2165 }
2166
2167 I915_WRITE(reg, val | PIPECONF_ENABLE);
2168 POSTING_READ(reg);
2169}
2170
2171/**
2172 * intel_disable_pipe - disable a pipe, asserting requirements
2173 * @crtc: crtc whose pipes is to be disabled
2174 *
2175 * Disable the pipe of @crtc, making sure that various hardware
2176 * specific requirements are met, if applicable, e.g. plane
2177 * disabled, panel fitter off, etc.
2178 *
2179 * Will wait until the pipe has shut down before returning.
2180 */
2181static void intel_disable_pipe(struct intel_crtc *crtc)
2182{
2183 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2184 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2185 enum i915_pipe pipe = crtc->pipe;
2186 int reg;
2187 u32 val;
2188
2189 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2190
2191 /*
2192 * Make sure planes won't keep trying to pump pixels to us,
2193 * or we might hang the display.
2194 */
2195 assert_planes_disabled(dev_priv, pipe);
2196 assert_cursor_disabled(dev_priv, pipe);
2197 assert_sprites_disabled(dev_priv, pipe);
2198
2199 reg = PIPECONF(cpu_transcoder);
2200 val = I915_READ(reg);
2201 if ((val & PIPECONF_ENABLE) == 0)
2202 return;
2203
2204 /*
2205 * Double wide has implications for planes
2206 * so best keep it disabled when not needed.
2207 */
2208 if (crtc->config->double_wide)
2209 val &= ~PIPECONF_DOUBLE_WIDE;
2210
2211 /* Don't disable pipe or pipe PLLs if needed */
2212 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2213 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2214 val &= ~PIPECONF_ENABLE;
2215
2216 I915_WRITE(reg, val);
2217 if ((val & PIPECONF_ENABLE) == 0)
2218 intel_wait_for_pipe_off(crtc);
2219}
2220
2221static bool need_vtd_wa(struct drm_device *dev)
2222{
2223#ifdef CONFIG_INTEL_IOMMU
2224 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2225 return true;
2226#endif
2227 return false;
2228}
2229
2230unsigned int
2231intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2232 uint64_t fb_format_modifier, unsigned int plane)
2233{
2234 unsigned int tile_height;
2235 uint32_t pixel_bytes;
2236
2237 switch (fb_format_modifier) {
2238 case DRM_FORMAT_MOD_NONE:
2239 tile_height = 1;
2240 break;
2241 case I915_FORMAT_MOD_X_TILED:
2242 tile_height = IS_GEN2(dev) ? 16 : 8;
2243 break;
2244 case I915_FORMAT_MOD_Y_TILED:
2245 tile_height = 32;
2246 break;
2247 case I915_FORMAT_MOD_Yf_TILED:
2248 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2249 switch (pixel_bytes) {
2250 default:
2251 case 1:
2252 tile_height = 64;
2253 break;
2254 case 2:
2255 case 4:
2256 tile_height = 32;
2257 break;
2258 case 8:
2259 tile_height = 16;
2260 break;
2261 case 16:
2262 WARN_ONCE(1,
2263 "128-bit pixels are not supported for display!");
2264 tile_height = 16;
2265 break;
2266 }
2267 break;
2268 default:
2269 MISSING_CASE(fb_format_modifier);
2270 tile_height = 1;
2271 break;
2272 }
2273
2274 return tile_height;
2275}
2276
2277unsigned int
2278intel_fb_align_height(struct drm_device *dev, unsigned int height,
2279 uint32_t pixel_format, uint64_t fb_format_modifier)
2280{
2281#ifdef __NetBSD__ /* XXX ALIGN means something else. */
2282 return round_up(height, intel_tile_height(dev, pixel_format,
2283 fb_format_modifier, 0));
2284#else
2285 return ALIGN(height, intel_tile_height(dev, pixel_format,
2286 fb_format_modifier, 0));
2287#endif
2288}
2289
2290static int
2291intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2292 const struct drm_plane_state *plane_state)
2293{
2294 struct intel_rotation_info *info = &view->rotation_info;
2295 unsigned int tile_height, tile_pitch;
2296
2297 *view = i915_ggtt_view_normal;
2298
2299 if (!plane_state)
2300 return 0;
2301
2302 if (!intel_rotation_90_or_270(plane_state->rotation))
2303 return 0;
2304
2305 *view = i915_ggtt_view_rotated;
2306
2307 info->height = fb->height;
2308 info->pixel_format = fb->pixel_format;
2309 info->pitch = fb->pitches[0];
2310 info->uv_offset = fb->offsets[1];
2311 info->fb_modifier = fb->modifier[0];
2312
2313 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2314 fb->modifier[0], 0);
2315 tile_pitch = PAGE_SIZE / tile_height;
2316 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2317 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2318 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2319
2320 if (info->pixel_format == DRM_FORMAT_NV12) {
2321 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2322 fb->modifier[0], 1);
2323 tile_pitch = PAGE_SIZE / tile_height;
2324 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2325 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2326 tile_height);
2327 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2328 PAGE_SIZE;
2329 }
2330
2331 return 0;
2332}
2333
2334static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2335{
2336 if (INTEL_INFO(dev_priv)->gen >= 9)
2337 return 256 * 1024;
2338 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2339 IS_VALLEYVIEW(dev_priv))
2340 return 128 * 1024;
2341 else if (INTEL_INFO(dev_priv)->gen >= 4)
2342 return 4 * 1024;
2343 else
2344 return 0;
2345}
2346
2347int
2348intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2349 struct drm_framebuffer *fb,
2350 const struct drm_plane_state *plane_state,
2351 struct intel_engine_cs *pipelined,
2352 struct drm_i915_gem_request **pipelined_request)
2353{
2354 struct drm_device *dev = fb->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2357 struct i915_ggtt_view view;
2358 u32 alignment;
2359 int ret;
2360
2361 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2362
2363 switch (fb->modifier[0]) {
2364 case DRM_FORMAT_MOD_NONE:
2365 alignment = intel_linear_alignment(dev_priv);
2366 break;
2367 case I915_FORMAT_MOD_X_TILED:
2368 if (INTEL_INFO(dev)->gen >= 9)
2369 alignment = 256 * 1024;
2370 else {
2371 /* pin() will align the object as required by fence */
2372 alignment = 0;
2373 }
2374 break;
2375 case I915_FORMAT_MOD_Y_TILED:
2376 case I915_FORMAT_MOD_Yf_TILED:
2377 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2378 "Y tiling bo slipped through, driver bug!\n"))
2379 return -EINVAL;
2380 alignment = 1 * 1024 * 1024;
2381 break;
2382 default:
2383 MISSING_CASE(fb->modifier[0]);
2384 return -EINVAL;
2385 }
2386
2387 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2388 if (ret)
2389 return ret;
2390
2391 /* Note that the w/a also requires 64 PTE of padding following the
2392 * bo. We currently fill all unused PTE with the shadow page and so
2393 * we should always have valid PTE following the scanout preventing
2394 * the VT-d warning.
2395 */
2396 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2397 alignment = 256 * 1024;
2398
2399 /*
2400 * Global gtt pte registers are special registers which actually forward
2401 * writes to a chunk of system memory. Which means that there is no risk
2402 * that the register values disappear as soon as we call
2403 * intel_runtime_pm_put(), so it is correct to wrap only the
2404 * pin/unpin/fence and not more.
2405 */
2406 intel_runtime_pm_get(dev_priv);
2407
2408 dev_priv->mm.interruptible = false;
2409 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2410 pipelined_request, &view);
2411 if (ret)
2412 goto err_interruptible;
2413
2414 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2415 * fence, whereas 965+ only requires a fence if using
2416 * framebuffer compression. For simplicity, we always install
2417 * a fence as the cost is not that onerous.
2418 */
2419 if (view.type == I915_GGTT_VIEW_NORMAL) {
2420 ret = i915_gem_object_get_fence(obj);
2421 if (ret == -EDEADLK) {
2422 /*
2423 * -EDEADLK means there are no free fences
2424 * no pending flips.
2425 *
2426 * This is propagated to atomic, but it uses
2427 * -EDEADLK to force a locking recovery, so
2428 * change the returned error to -EBUSY.
2429 */
2430 ret = -EBUSY;
2431 goto err_unpin;
2432 } else if (ret)
2433 goto err_unpin;
2434
2435 i915_gem_object_pin_fence(obj);
2436 }
2437
2438 dev_priv->mm.interruptible = true;
2439 intel_runtime_pm_put(dev_priv);
2440 return 0;
2441
2442err_unpin:
2443 i915_gem_object_unpin_from_display_plane(obj, &view);
2444err_interruptible:
2445 dev_priv->mm.interruptible = true;
2446 intel_runtime_pm_put(dev_priv);
2447 return ret;
2448}
2449
2450static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2451 const struct drm_plane_state *plane_state)
2452{
2453 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2454 struct i915_ggtt_view view;
2455 int ret;
2456
2457 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2458
2459 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2460 WARN_ONCE(ret, "Couldn't get view from plane state!");
2461
2462 if (view.type == I915_GGTT_VIEW_NORMAL)
2463 i915_gem_object_unpin_fence(obj);
2464
2465 i915_gem_object_unpin_from_display_plane(obj, &view);
2466}
2467
2468/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2469 * is assumed to be a power-of-two. */
2470unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2471 int *x, int *y,
2472 unsigned int tiling_mode,
2473 unsigned int cpp,
2474 unsigned int pitch)
2475{
2476 if (tiling_mode != I915_TILING_NONE) {
2477 unsigned int tile_rows, tiles;
2478
2479 tile_rows = *y / 8;
2480 *y %= 8;
2481
2482 tiles = *x / (512/cpp);
2483 *x %= 512/cpp;
2484
2485 return tile_rows * pitch * 8 + tiles * 4096;
2486 } else {
2487 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2488 unsigned int offset;
2489
2490 offset = *y * pitch + *x * cpp;
2491 *y = (offset & alignment) / pitch;
2492 *x = ((offset & alignment) - *y * pitch) / cpp;
2493 return offset & ~alignment;
2494 }
2495}
2496
2497static int i9xx_format_to_fourcc(int format)
2498{
2499 switch (format) {
2500 case DISPPLANE_8BPP:
2501 return DRM_FORMAT_C8;
2502 case DISPPLANE_BGRX555:
2503 return DRM_FORMAT_XRGB1555;
2504 case DISPPLANE_BGRX565:
2505 return DRM_FORMAT_RGB565;
2506 default:
2507 case DISPPLANE_BGRX888:
2508 return DRM_FORMAT_XRGB8888;
2509 case DISPPLANE_RGBX888:
2510 return DRM_FORMAT_XBGR8888;
2511 case DISPPLANE_BGRX101010:
2512 return DRM_FORMAT_XRGB2101010;
2513 case DISPPLANE_RGBX101010:
2514 return DRM_FORMAT_XBGR2101010;
2515 }
2516}
2517
2518static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2519{
2520 switch (format) {
2521 case PLANE_CTL_FORMAT_RGB_565:
2522 return DRM_FORMAT_RGB565;
2523 default:
2524 case PLANE_CTL_FORMAT_XRGB_8888:
2525 if (rgb_order) {
2526 if (alpha)
2527 return DRM_FORMAT_ABGR8888;
2528 else
2529 return DRM_FORMAT_XBGR8888;
2530 } else {
2531 if (alpha)
2532 return DRM_FORMAT_ARGB8888;
2533 else
2534 return DRM_FORMAT_XRGB8888;
2535 }
2536 case PLANE_CTL_FORMAT_XRGB_2101010:
2537 if (rgb_order)
2538 return DRM_FORMAT_XBGR2101010;
2539 else
2540 return DRM_FORMAT_XRGB2101010;
2541 }
2542}
2543
2544static bool
2545intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2546 struct intel_initial_plane_config *plane_config)
2547{
2548 struct drm_device *dev = crtc->base.dev;
2549 struct drm_i915_private *dev_priv = to_i915(dev);
2550 struct drm_i915_gem_object *obj = NULL;
2551 static const struct drm_mode_fb_cmd2 zero_mode_cmd;
2552 struct drm_mode_fb_cmd2 mode_cmd = zero_mode_cmd;
2553 struct drm_framebuffer *fb = &plane_config->fb->base;
2554 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2555 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2556 PAGE_SIZE);
2557
2558 size_aligned -= base_aligned;
2559
2560 if (plane_config->size == 0)
2561 return false;
2562
2563 /* If the FB is too big, just don't use it since fbdev is not very
2564 * important and we should probably use that space with FBC or other
2565 * features. */
2566 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2567 return false;
2568
2569 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2570 base_aligned,
2571 base_aligned,
2572 size_aligned);
2573 if (!obj)
2574 return false;
2575
2576 obj->tiling_mode = plane_config->tiling;
2577 if (obj->tiling_mode == I915_TILING_X)
2578 obj->stride = fb->pitches[0];
2579
2580 mode_cmd.pixel_format = fb->pixel_format;
2581 mode_cmd.width = fb->width;
2582 mode_cmd.height = fb->height;
2583 mode_cmd.pitches[0] = fb->pitches[0];
2584 mode_cmd.modifier[0] = fb->modifier[0];
2585 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2586
2587 mutex_lock(&dev->struct_mutex);
2588 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2589 &mode_cmd, obj)) {
2590 DRM_DEBUG_KMS("intel fb init failed\n");
2591 goto out_unref_obj;
2592 }
2593 mutex_unlock(&dev->struct_mutex);
2594
2595 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2596 return true;
2597
2598out_unref_obj:
2599 drm_gem_object_unreference(&obj->base);
2600 mutex_unlock(&dev->struct_mutex);
2601 return false;
2602}
2603
2604/* Update plane->state->fb to match plane->fb after driver-internal updates */
2605static void
2606update_state_fb(struct drm_plane *plane)
2607{
2608 if (plane->fb == plane->state->fb)
2609 return;
2610
2611 if (plane->state->fb)
2612 drm_framebuffer_unreference(plane->state->fb);
2613 plane->state->fb = plane->fb;
2614 if (plane->state->fb)
2615 drm_framebuffer_reference(plane->state->fb);
2616}
2617
2618static void
2619intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2620 struct intel_initial_plane_config *plane_config)
2621{
2622 struct drm_device *dev = intel_crtc->base.dev;
2623 struct drm_i915_private *dev_priv = dev->dev_private;
2624 struct drm_crtc *c;
2625 struct intel_crtc *i;
2626 struct drm_i915_gem_object *obj;
2627 struct drm_plane *primary = intel_crtc->base.primary;
2628 struct drm_plane_state *plane_state = primary->state;
2629 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2630 struct intel_plane *intel_plane = to_intel_plane(primary);
2631 struct drm_framebuffer *fb;
2632
2633 if (!plane_config->fb)
2634 return;
2635
2636 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2637 fb = &plane_config->fb->base;
2638 goto valid_fb;
2639 }
2640
2641 kfree(plane_config->fb);
2642
2643 /*
2644 * Failed to alloc the obj, check to see if we should share
2645 * an fb with another CRTC instead
2646 */
2647 for_each_crtc(dev, c) {
2648 i = to_intel_crtc(c);
2649
2650 if (c == &intel_crtc->base)
2651 continue;
2652
2653 if (!i->active)
2654 continue;
2655
2656 fb = c->primary->fb;
2657 if (!fb)
2658 continue;
2659
2660 obj = intel_fb_obj(fb);
2661 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2662 drm_framebuffer_reference(fb);
2663 goto valid_fb;
2664 }
2665 }
2666
2667 /*
2668 * We've failed to reconstruct the BIOS FB. Current display state
2669 * indicates that the primary plane is visible, but has a NULL FB,
2670 * which will lead to problems later if we don't fix it up. The
2671 * simplest solution is to just disable the primary plane now and
2672 * pretend the BIOS never had it enabled.
2673 */
2674 to_intel_plane_state(plane_state)->visible = false;
2675 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2676 intel_pre_disable_primary(&intel_crtc->base);
2677 intel_plane->disable_plane(primary, &intel_crtc->base);
2678
2679 return;
2680
2681valid_fb:
2682 plane_state->src_x = 0;
2683 plane_state->src_y = 0;
2684 plane_state->src_w = fb->width << 16;
2685 plane_state->src_h = fb->height << 16;
2686
2687 plane_state->crtc_x = 0;
2688 plane_state->crtc_y = 0;
2689 plane_state->crtc_w = fb->width;
2690 plane_state->crtc_h = fb->height;
2691
2692 obj = intel_fb_obj(fb);
2693 if (obj->tiling_mode != I915_TILING_NONE)
2694 dev_priv->preserve_bios_swizzle = true;
2695
2696 drm_framebuffer_reference(fb);
2697 primary->fb = primary->state->fb = fb;
2698 primary->crtc = primary->state->crtc = &intel_crtc->base;
2699 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2700 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2701}
2702
2703static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2704 struct drm_framebuffer *fb,
2705 int x, int y)
2706{
2707 struct drm_device *dev = crtc->dev;
2708 struct drm_i915_private *dev_priv = dev->dev_private;
2709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2710 struct drm_plane *primary = crtc->primary;
2711 bool visible = to_intel_plane_state(primary->state)->visible;
2712 struct drm_i915_gem_object *obj;
2713 int plane = intel_crtc->plane;
2714 unsigned long linear_offset;
2715 u32 dspcntr;
2716 u32 reg = DSPCNTR(plane);
2717 int pixel_size;
2718
2719 if (!visible || !fb) {
2720 I915_WRITE(reg, 0);
2721 if (INTEL_INFO(dev)->gen >= 4)
2722 I915_WRITE(DSPSURF(plane), 0);
2723 else
2724 I915_WRITE(DSPADDR(plane), 0);
2725 POSTING_READ(reg);
2726 return;
2727 }
2728
2729 obj = intel_fb_obj(fb);
2730 if (WARN_ON(obj == NULL))
2731 return;
2732
2733 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2734
2735 dspcntr = DISPPLANE_GAMMA_ENABLE;
2736
2737 dspcntr |= DISPLAY_PLANE_ENABLE;
2738
2739 if (INTEL_INFO(dev)->gen < 4) {
2740 if (intel_crtc->pipe == PIPE_B)
2741 dspcntr |= DISPPLANE_SEL_PIPE_B;
2742
2743 /* pipesrc and dspsize control the size that is scaled from,
2744 * which should always be the user's requested size.
2745 */
2746 I915_WRITE(DSPSIZE(plane),
2747 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2748 (intel_crtc->config->pipe_src_w - 1));
2749 I915_WRITE(DSPPOS(plane), 0);
2750 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2751 I915_WRITE(PRIMSIZE(plane),
2752 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2753 (intel_crtc->config->pipe_src_w - 1));
2754 I915_WRITE(PRIMPOS(plane), 0);
2755 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2756 }
2757
2758 switch (fb->pixel_format) {
2759 case DRM_FORMAT_C8:
2760 dspcntr |= DISPPLANE_8BPP;
2761 break;
2762 case DRM_FORMAT_XRGB1555:
2763 dspcntr |= DISPPLANE_BGRX555;
2764 break;
2765 case DRM_FORMAT_RGB565:
2766 dspcntr |= DISPPLANE_BGRX565;
2767 break;
2768 case DRM_FORMAT_XRGB8888:
2769 dspcntr |= DISPPLANE_BGRX888;
2770 break;
2771 case DRM_FORMAT_XBGR8888:
2772 dspcntr |= DISPPLANE_RGBX888;
2773 break;
2774 case DRM_FORMAT_XRGB2101010:
2775 dspcntr |= DISPPLANE_BGRX101010;
2776 break;
2777 case DRM_FORMAT_XBGR2101010:
2778 dspcntr |= DISPPLANE_RGBX101010;
2779 break;
2780 default:
2781 BUG();
2782 }
2783
2784 if (INTEL_INFO(dev)->gen >= 4 &&
2785 obj->tiling_mode != I915_TILING_NONE)
2786 dspcntr |= DISPPLANE_TILED;
2787
2788 if (IS_G4X(dev))
2789 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2790
2791 linear_offset = y * fb->pitches[0] + x * pixel_size;
2792
2793 if (INTEL_INFO(dev)->gen >= 4) {
2794 intel_crtc->dspaddr_offset =
2795 intel_gen4_compute_page_offset(dev_priv,
2796 &x, &y, obj->tiling_mode,
2797 pixel_size,
2798 fb->pitches[0]);
2799 linear_offset -= intel_crtc->dspaddr_offset;
2800 } else {
2801 intel_crtc->dspaddr_offset = linear_offset;
2802 }
2803
2804 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2805 dspcntr |= DISPPLANE_ROTATE_180;
2806
2807 x += (intel_crtc->config->pipe_src_w - 1);
2808 y += (intel_crtc->config->pipe_src_h - 1);
2809
2810 /* Finding the last pixel of the last line of the display
2811 data and adding to linear_offset*/
2812 linear_offset +=
2813 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2814 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2815 }
2816
2817 intel_crtc->adjusted_x = x;
2818 intel_crtc->adjusted_y = y;
2819
2820 I915_WRITE(reg, dspcntr);
2821
2822 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2823 if (INTEL_INFO(dev)->gen >= 4) {
2824 I915_WRITE(DSPSURF(plane),
2825 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2826 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2827 I915_WRITE(DSPLINOFF(plane), linear_offset);
2828 } else
2829 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2830 POSTING_READ(reg);
2831}
2832
2833static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2834 struct drm_framebuffer *fb,
2835 int x, int y)
2836{
2837 struct drm_device *dev = crtc->dev;
2838 struct drm_i915_private *dev_priv = dev->dev_private;
2839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2840 struct drm_plane *primary = crtc->primary;
2841 bool visible = to_intel_plane_state(primary->state)->visible;
2842 struct drm_i915_gem_object *obj;
2843 int plane = intel_crtc->plane;
2844 unsigned long linear_offset;
2845 u32 dspcntr;
2846 u32 reg = DSPCNTR(plane);
2847 int pixel_size;
2848
2849 if (!visible || !fb) {
2850 I915_WRITE(reg, 0);
2851 I915_WRITE(DSPSURF(plane), 0);
2852 POSTING_READ(reg);
2853 return;
2854 }
2855
2856 obj = intel_fb_obj(fb);
2857 if (WARN_ON(obj == NULL))
2858 return;
2859
2860 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2861
2862 dspcntr = DISPPLANE_GAMMA_ENABLE;
2863
2864 dspcntr |= DISPLAY_PLANE_ENABLE;
2865
2866 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2867 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2868
2869 switch (fb->pixel_format) {
2870 case DRM_FORMAT_C8:
2871 dspcntr |= DISPPLANE_8BPP;
2872 break;
2873 case DRM_FORMAT_RGB565:
2874 dspcntr |= DISPPLANE_BGRX565;
2875 break;
2876 case DRM_FORMAT_XRGB8888:
2877 dspcntr |= DISPPLANE_BGRX888;
2878 break;
2879 case DRM_FORMAT_XBGR8888:
2880 dspcntr |= DISPPLANE_RGBX888;
2881 break;
2882 case DRM_FORMAT_XRGB2101010:
2883 dspcntr |= DISPPLANE_BGRX101010;
2884 break;
2885 case DRM_FORMAT_XBGR2101010:
2886 dspcntr |= DISPPLANE_RGBX101010;
2887 break;
2888 default:
2889 BUG();
2890 }
2891
2892 if (obj->tiling_mode != I915_TILING_NONE)
2893 dspcntr |= DISPPLANE_TILED;
2894
2895 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2896 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2897
2898 linear_offset = y * fb->pitches[0] + x * pixel_size;
2899 intel_crtc->dspaddr_offset =
2900 intel_gen4_compute_page_offset(dev_priv,
2901 &x, &y, obj->tiling_mode,
2902 pixel_size,
2903 fb->pitches[0]);
2904 linear_offset -= intel_crtc->dspaddr_offset;
2905 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2906 dspcntr |= DISPPLANE_ROTATE_180;
2907
2908 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2909 x += (intel_crtc->config->pipe_src_w - 1);
2910 y += (intel_crtc->config->pipe_src_h - 1);
2911
2912 /* Finding the last pixel of the last line of the display
2913 data and adding to linear_offset*/
2914 linear_offset +=
2915 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2916 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2917 }
2918 }
2919
2920 intel_crtc->adjusted_x = x;
2921 intel_crtc->adjusted_y = y;
2922
2923 I915_WRITE(reg, dspcntr);
2924
2925 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2926 I915_WRITE(DSPSURF(plane),
2927 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2928 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2929 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2930 } else {
2931 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2932 I915_WRITE(DSPLINOFF(plane), linear_offset);
2933 }
2934 POSTING_READ(reg);
2935}
2936
2937u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2938 uint32_t pixel_format)
2939{
2940 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2941
2942 /*
2943 * The stride is either expressed as a multiple of 64 bytes
2944 * chunks for linear buffers or in number of tiles for tiled
2945 * buffers.
2946 */
2947 switch (fb_modifier) {
2948 case DRM_FORMAT_MOD_NONE:
2949 return 64;
2950 case I915_FORMAT_MOD_X_TILED:
2951 if (INTEL_INFO(dev)->gen == 2)
2952 return 128;
2953 return 512;
2954 case I915_FORMAT_MOD_Y_TILED:
2955 /* No need to check for old gens and Y tiling since this is
2956 * about the display engine and those will be blocked before
2957 * we get here.
2958 */
2959 return 128;
2960 case I915_FORMAT_MOD_Yf_TILED:
2961 if (bits_per_pixel == 8)
2962 return 64;
2963 else
2964 return 128;
2965 default:
2966 MISSING_CASE(fb_modifier);
2967 return 64;
2968 }
2969}
2970
2971u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2972 struct drm_i915_gem_object *obj,
2973 unsigned int plane)
2974{
2975 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2976 struct i915_vma *vma;
2977 u64 offset;
2978
2979 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2980 view = &i915_ggtt_view_rotated;
2981
2982 vma = i915_gem_obj_to_ggtt_view(obj, view);
2983 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2984 view->type))
2985 return -1;
2986
2987 offset = vma->node.start;
2988
2989 if (plane == 1) {
2990 offset += vma->ggtt_view.rotation_info.uv_start_page *
2991 PAGE_SIZE;
2992 }
2993
2994 WARN_ON(upper_32_bits(offset));
2995
2996 return lower_32_bits(offset);
2997}
2998
2999static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3000{
3001 struct drm_device *dev = intel_crtc->base.dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003
3004 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3005 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3006 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3007}
3008
3009/*
3010 * This function detaches (aka. unbinds) unused scalers in hardware
3011 */
3012static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3013{
3014 struct intel_crtc_scaler_state *scaler_state;
3015 int i;
3016
3017 scaler_state = &intel_crtc->config->scaler_state;
3018
3019 /* loop through and disable scalers that aren't in use */
3020 for (i = 0; i < intel_crtc->num_scalers; i++) {
3021 if (!scaler_state->scalers[i].in_use)
3022 skl_detach_scaler(intel_crtc, i);
3023 }
3024}
3025
3026u32 skl_plane_ctl_format(uint32_t pixel_format)
3027{
3028 switch (pixel_format) {
3029 case DRM_FORMAT_C8:
3030 return PLANE_CTL_FORMAT_INDEXED;
3031 case DRM_FORMAT_RGB565:
3032 return PLANE_CTL_FORMAT_RGB_565;
3033 case DRM_FORMAT_XBGR8888:
3034 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3035 case DRM_FORMAT_XRGB8888:
3036 return PLANE_CTL_FORMAT_XRGB_8888;
3037 /*
3038 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3039 * to be already pre-multiplied. We need to add a knob (or a different
3040 * DRM_FORMAT) for user-space to configure that.
3041 */
3042 case DRM_FORMAT_ABGR8888:
3043 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3044 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3045 case DRM_FORMAT_ARGB8888:
3046 return PLANE_CTL_FORMAT_XRGB_8888 |
3047 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3048 case DRM_FORMAT_XRGB2101010:
3049 return PLANE_CTL_FORMAT_XRGB_2101010;
3050 case DRM_FORMAT_XBGR2101010:
3051 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3052 case DRM_FORMAT_YUYV:
3053 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3054 case DRM_FORMAT_YVYU:
3055 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3056 case DRM_FORMAT_UYVY:
3057 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3058 case DRM_FORMAT_VYUY:
3059 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3060 default:
3061 MISSING_CASE(pixel_format);
3062 }
3063
3064 return 0;
3065}
3066
3067u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3068{
3069 switch (fb_modifier) {
3070 case DRM_FORMAT_MOD_NONE:
3071 break;
3072 case I915_FORMAT_MOD_X_TILED:
3073 return PLANE_CTL_TILED_X;
3074 case I915_FORMAT_MOD_Y_TILED:
3075 return PLANE_CTL_TILED_Y;
3076 case I915_FORMAT_MOD_Yf_TILED:
3077 return PLANE_CTL_TILED_YF;
3078 default:
3079 MISSING_CASE(fb_modifier);
3080 }
3081
3082 return 0;
3083}
3084
3085u32 skl_plane_ctl_rotation(unsigned int rotation)
3086{
3087 switch (rotation) {
3088 case BIT(DRM_ROTATE_0):
3089 break;
3090 /*
3091 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3092 * while i915 HW rotation is clockwise, thats why this swapping.
3093 */
3094 case BIT(DRM_ROTATE_90):
3095 return PLANE_CTL_ROTATE_270;
3096 case BIT(DRM_ROTATE_180):
3097 return PLANE_CTL_ROTATE_180;
3098 case BIT(DRM_ROTATE_270):
3099 return PLANE_CTL_ROTATE_90;
3100 default:
3101 MISSING_CASE(rotation);
3102 }
3103
3104 return 0;
3105}
3106
3107static void skylake_update_primary_plane(struct drm_crtc *crtc,
3108 struct drm_framebuffer *fb,
3109 int x, int y)
3110{
3111 struct drm_device *dev = crtc->dev;
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3114 struct drm_plane *plane = crtc->primary;
3115 bool visible = to_intel_plane_state(plane->state)->visible;
3116 struct drm_i915_gem_object *obj;
3117 int pipe = intel_crtc->pipe;
3118 u32 plane_ctl, stride_div, stride;
3119 u32 tile_height, plane_offset, plane_size;
3120 unsigned int rotation;
3121 int x_offset, y_offset;
3122 u32 surf_addr;
3123 struct intel_crtc_state *crtc_state = intel_crtc->config;
3124 struct intel_plane_state *plane_state;
3125 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3126 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3127 int scaler_id = -1;
3128
3129 plane_state = to_intel_plane_state(plane->state);
3130
3131 if (!visible || !fb) {
3132 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3133 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3134 POSTING_READ(PLANE_CTL(pipe, 0));
3135 return;
3136 }
3137
3138 plane_ctl = PLANE_CTL_ENABLE |
3139 PLANE_CTL_PIPE_GAMMA_ENABLE |
3140 PLANE_CTL_PIPE_CSC_ENABLE;
3141
3142 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3143 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3144 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3145
3146 rotation = plane->state->rotation;
3147 plane_ctl |= skl_plane_ctl_rotation(rotation);
3148
3149 obj = intel_fb_obj(fb);
3150 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3151 fb->pixel_format);
3152 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3153
3154 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3155
3156 scaler_id = plane_state->scaler_id;
3157 src_x = plane_state->src.x1 >> 16;
3158 src_y = plane_state->src.y1 >> 16;
3159 src_w = drm_rect_width(&plane_state->src) >> 16;
3160 src_h = drm_rect_height(&plane_state->src) >> 16;
3161 dst_x = plane_state->dst.x1;
3162 dst_y = plane_state->dst.y1;
3163 dst_w = drm_rect_width(&plane_state->dst);
3164 dst_h = drm_rect_height(&plane_state->dst);
3165
3166 WARN_ON(x != src_x || y != src_y);
3167
3168 if (intel_rotation_90_or_270(rotation)) {
3169 /* stride = Surface height in tiles */
3170 tile_height = intel_tile_height(dev, fb->pixel_format,
3171 fb->modifier[0], 0);
3172 stride = DIV_ROUND_UP(fb->height, tile_height);
3173 x_offset = stride * tile_height - y - src_h;
3174 y_offset = x;
3175 plane_size = (src_w - 1) << 16 | (src_h - 1);
3176 } else {
3177 stride = fb->pitches[0] / stride_div;
3178 x_offset = x;
3179 y_offset = y;
3180 plane_size = (src_h - 1) << 16 | (src_w - 1);
3181 }
3182 plane_offset = y_offset << 16 | x_offset;
3183
3184 intel_crtc->adjusted_x = x_offset;
3185 intel_crtc->adjusted_y = y_offset;
3186
3187 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3188 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3189 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3190 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3191
3192 if (scaler_id >= 0) {
3193 uint32_t ps_ctrl = 0;
3194
3195 WARN_ON(!dst_w || !dst_h);
3196 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3197 crtc_state->scaler_state.scalers[scaler_id].mode;
3198 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3199 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3200 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3201 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3202 I915_WRITE(PLANE_POS(pipe, 0), 0);
3203 } else {
3204 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3205 }
3206
3207 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3208
3209 POSTING_READ(PLANE_SURF(pipe, 0));
3210}
3211
3212/* Assume fb object is pinned & idle & fenced and just update base pointers */
3213static int
3214intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3215 int x, int y, enum mode_set_atomic state)
3216{
3217 struct drm_device *dev = crtc->dev;
3218 struct drm_i915_private *dev_priv = dev->dev_private;
3219
3220 if (dev_priv->fbc.disable_fbc)
3221 dev_priv->fbc.disable_fbc(dev_priv);
3222
3223 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3224
3225 return 0;
3226}
3227
3228static void intel_complete_page_flips(struct drm_device *dev)
3229{
3230 struct drm_crtc *crtc;
3231
3232 for_each_crtc(dev, crtc) {
3233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3234 enum plane plane = intel_crtc->plane;
3235
3236 intel_prepare_page_flip(dev, plane);
3237 intel_finish_page_flip_plane(dev, plane);
3238 }
3239}
3240
3241static void intel_update_primary_planes(struct drm_device *dev)
3242{
3243 struct drm_crtc *crtc;
3244
3245 for_each_crtc(dev, crtc) {
3246 struct intel_plane *plane = to_intel_plane(crtc->primary);
3247 struct intel_plane_state *plane_state;
3248
3249 drm_modeset_lock_crtc(crtc, &plane->base);
3250
3251 plane_state = to_intel_plane_state(plane->base.state);
3252
3253 if (plane_state->base.fb)
3254 plane->commit_plane(&plane->base, plane_state);
3255
3256 drm_modeset_unlock_crtc(crtc);
3257 }
3258}
3259
3260void intel_prepare_reset(struct drm_device *dev)
3261{
3262 /* no reset support for gen2 */
3263 if (IS_GEN2(dev))
3264 return;
3265
3266 /* reset doesn't touch the display */
3267 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3268 return;
3269
3270 drm_modeset_lock_all(dev);
3271 /*
3272 * Disabling the crtcs gracefully seems nicer. Also the
3273 * g33 docs say we should at least disable all the planes.
3274 */
3275 intel_display_suspend(dev);
3276}
3277
3278void intel_finish_reset(struct drm_device *dev)
3279{
3280 struct drm_i915_private *dev_priv = to_i915(dev);
3281
3282 /*
3283 * Flips in the rings will be nuked by the reset,
3284 * so complete all pending flips so that user space
3285 * will get its events and not get stuck.
3286 */
3287 intel_complete_page_flips(dev);
3288
3289 /* no reset support for gen2 */
3290 if (IS_GEN2(dev))
3291 return;
3292
3293 /* reset doesn't touch the display */
3294 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3295 /*
3296 * Flips in the rings have been nuked by the reset,
3297 * so update the base address of all primary
3298 * planes to the the last fb to make sure we're
3299 * showing the correct fb after a reset.
3300 *
3301 * FIXME: Atomic will make this obsolete since we won't schedule
3302 * CS-based flips (which might get lost in gpu resets) any more.
3303 */
3304 intel_update_primary_planes(dev);
3305 return;
3306 }
3307
3308 /*
3309 * The display has been reset as well,
3310 * so need a full re-initialization.
3311 */
3312 intel_runtime_pm_disable_interrupts(dev_priv);
3313 intel_runtime_pm_enable_interrupts(dev_priv);
3314
3315 intel_modeset_init_hw(dev);
3316
3317 spin_lock_irq(&dev_priv->irq_lock);
3318 if (dev_priv->display.hpd_irq_setup)
3319 dev_priv->display.hpd_irq_setup(dev);
3320 spin_unlock_irq(&dev_priv->irq_lock);
3321
3322 intel_display_resume(dev);
3323
3324 intel_hpd_init(dev_priv);
3325
3326 drm_modeset_unlock_all(dev);
3327}
3328
3329static void
3330intel_finish_fb(struct drm_framebuffer *old_fb)
3331{
3332 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3333 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3334 bool was_interruptible = dev_priv->mm.interruptible;
3335 int ret;
3336
3337 /* Big Hammer, we also need to ensure that any pending
3338 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3339 * current scanout is retired before unpinning the old
3340 * framebuffer. Note that we rely on userspace rendering
3341 * into the buffer attached to the pipe they are waiting
3342 * on. If not, userspace generates a GPU hang with IPEHR
3343 * point to the MI_WAIT_FOR_EVENT.
3344 *
3345 * This should only fail upon a hung GPU, in which case we
3346 * can safely continue.
3347 */
3348 dev_priv->mm.interruptible = false;
3349 ret = i915_gem_object_wait_rendering(obj, true);
3350 dev_priv->mm.interruptible = was_interruptible;
3351
3352 WARN_ON(ret);
3353}
3354
3355static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3356{
3357 struct drm_device *dev = crtc->dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3360 bool pending;
3361
3362 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3363 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3364 return false;
3365
3366 spin_lock_irq(&dev->event_lock);
3367 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3368 spin_unlock_irq(&dev->event_lock);
3369
3370 return pending;
3371}
3372
3373static void intel_update_pipe_config(struct intel_crtc *crtc,
3374 struct intel_crtc_state *old_crtc_state)
3375{
3376 struct drm_device *dev = crtc->base.dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct intel_crtc_state *pipe_config =
3379 to_intel_crtc_state(crtc->base.state);
3380
3381 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3382 crtc->base.mode = crtc->base.state->mode;
3383
3384 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3385 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3386 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3387
3388 if (HAS_DDI(dev))
3389 intel_set_pipe_csc(&crtc->base);
3390
3391 /*
3392 * Update pipe size and adjust fitter if needed: the reason for this is
3393 * that in compute_mode_changes we check the native mode (not the pfit
3394 * mode) to see if we can flip rather than do a full mode set. In the
3395 * fastboot case, we'll flip, but if we don't update the pipesrc and
3396 * pfit state, we'll end up with a big fb scanned out into the wrong
3397 * sized surface.
3398 */
3399
3400 I915_WRITE(PIPESRC(crtc->pipe),
3401 ((pipe_config->pipe_src_w - 1) << 16) |
3402 (pipe_config->pipe_src_h - 1));
3403
3404 /* on skylake this is done by detaching scalers */
3405 if (INTEL_INFO(dev)->gen >= 9) {
3406 skl_detach_scalers(crtc);
3407
3408 if (pipe_config->pch_pfit.enabled)
3409 skylake_pfit_enable(crtc);
3410 } else if (HAS_PCH_SPLIT(dev)) {
3411 if (pipe_config->pch_pfit.enabled)
3412 ironlake_pfit_enable(crtc);
3413 else if (old_crtc_state->pch_pfit.enabled)
3414 ironlake_pfit_disable(crtc, true);
3415 }
3416}
3417
3418static void intel_fdi_normal_train(struct drm_crtc *crtc)
3419{
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 int pipe = intel_crtc->pipe;
3424 u32 reg, temp;
3425
3426 /* enable normal train */
3427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 if (IS_IVYBRIDGE(dev)) {
3430 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3431 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3432 } else {
3433 temp &= ~FDI_LINK_TRAIN_NONE;
3434 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3435 }
3436 I915_WRITE(reg, temp);
3437
3438 reg = FDI_RX_CTL(pipe);
3439 temp = I915_READ(reg);
3440 if (HAS_PCH_CPT(dev)) {
3441 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3442 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3443 } else {
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_NONE;
3446 }
3447 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3448
3449 /* wait one idle pattern time */
3450 POSTING_READ(reg);
3451 udelay(1000);
3452
3453 /* IVB wants error correction enabled */
3454 if (IS_IVYBRIDGE(dev))
3455 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3456 FDI_FE_ERRC_ENABLE);
3457}
3458
3459/* The FDI link training functions for ILK/Ibexpeak. */
3460static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3461{
3462 struct drm_device *dev = crtc->dev;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465 int pipe = intel_crtc->pipe;
3466 u32 reg, temp, tries;
3467
3468 /* FDI needs bits from pipe first */
3469 assert_pipe_enabled(dev_priv, pipe);
3470
3471 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3472 for train result */
3473 reg = FDI_RX_IMR(pipe);
3474 temp = I915_READ(reg);
3475 temp &= ~FDI_RX_SYMBOL_LOCK;
3476 temp &= ~FDI_RX_BIT_LOCK;
3477 I915_WRITE(reg, temp);
3478 I915_READ(reg);
3479 udelay(150);
3480
3481 /* enable CPU FDI TX and PCH FDI RX */
3482 reg = FDI_TX_CTL(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3485 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3486 temp &= ~FDI_LINK_TRAIN_NONE;
3487 temp |= FDI_LINK_TRAIN_PATTERN_1;
3488 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3489
3490 reg = FDI_RX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 temp &= ~FDI_LINK_TRAIN_NONE;
3493 temp |= FDI_LINK_TRAIN_PATTERN_1;
3494 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3495
3496 POSTING_READ(reg);
3497 udelay(150);
3498
3499 /* Ironlake workaround, enable clock pointer after FDI enable*/
3500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3501 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3502 FDI_RX_PHASE_SYNC_POINTER_EN);
3503
3504 reg = FDI_RX_IIR(pipe);
3505 for (tries = 0; tries < 5; tries++) {
3506 temp = I915_READ(reg);
3507 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3508
3509 if ((temp & FDI_RX_BIT_LOCK)) {
3510 DRM_DEBUG_KMS("FDI train 1 done.\n");
3511 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3512 break;
3513 }
3514 }
3515 if (tries == 5)
3516 DRM_ERROR("FDI train 1 fail!\n");
3517
3518 /* Train 2 */
3519 reg = FDI_TX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_LINK_TRAIN_NONE;
3522 temp |= FDI_LINK_TRAIN_PATTERN_2;
3523 I915_WRITE(reg, temp);
3524
3525 reg = FDI_RX_CTL(pipe);
3526 temp = I915_READ(reg);
3527 temp &= ~FDI_LINK_TRAIN_NONE;
3528 temp |= FDI_LINK_TRAIN_PATTERN_2;
3529 I915_WRITE(reg, temp);
3530
3531 POSTING_READ(reg);
3532 udelay(150);
3533
3534 reg = FDI_RX_IIR(pipe);
3535 for (tries = 0; tries < 5; tries++) {
3536 temp = I915_READ(reg);
3537 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3538
3539 if (temp & FDI_RX_SYMBOL_LOCK) {
3540 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3541 DRM_DEBUG_KMS("FDI train 2 done.\n");
3542 break;
3543 }
3544 }
3545 if (tries == 5)
3546 DRM_ERROR("FDI train 2 fail!\n");
3547
3548 DRM_DEBUG_KMS("FDI train done\n");
3549
3550}
3551
3552static const int snb_b_fdi_train_param[] = {
3553 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3554 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3555 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3556 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3557};
3558
3559/* The FDI link training functions for SNB/Cougarpoint. */
3560static void gen6_fdi_link_train(struct drm_crtc *crtc)
3561{
3562 struct drm_device *dev = crtc->dev;
3563 struct drm_i915_private *dev_priv = dev->dev_private;
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565 int pipe = intel_crtc->pipe;
3566 u32 reg, temp, i, retry;
3567
3568 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3569 for train result */
3570 reg = FDI_RX_IMR(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~FDI_RX_SYMBOL_LOCK;
3573 temp &= ~FDI_RX_BIT_LOCK;
3574 I915_WRITE(reg, temp);
3575
3576 POSTING_READ(reg);
3577 udelay(150);
3578
3579 /* enable CPU FDI TX and PCH FDI RX */
3580 reg = FDI_TX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3583 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_1;
3586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3587 /* SNB-B */
3588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3589 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3590
3591 I915_WRITE(FDI_RX_MISC(pipe),
3592 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3593
3594 reg = FDI_RX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 if (HAS_PCH_CPT(dev)) {
3597 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3598 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3599 } else {
3600 temp &= ~FDI_LINK_TRAIN_NONE;
3601 temp |= FDI_LINK_TRAIN_PATTERN_1;
3602 }
3603 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3604
3605 POSTING_READ(reg);
3606 udelay(150);
3607
3608 for (i = 0; i < 4; i++) {
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3612 temp |= snb_b_fdi_train_param[i];
3613 I915_WRITE(reg, temp);
3614
3615 POSTING_READ(reg);
3616 udelay(500);
3617
3618 for (retry = 0; retry < 5; retry++) {
3619 reg = FDI_RX_IIR(pipe);
3620 temp = I915_READ(reg);
3621 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3622 if (temp & FDI_RX_BIT_LOCK) {
3623 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3624 DRM_DEBUG_KMS("FDI train 1 done.\n");
3625 break;
3626 }
3627 udelay(50);
3628 }
3629 if (retry < 5)
3630 break;
3631 }
3632 if (i == 4)
3633 DRM_ERROR("FDI train 1 fail!\n");
3634
3635 /* Train 2 */
3636 reg = FDI_TX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_LINK_TRAIN_NONE;
3639 temp |= FDI_LINK_TRAIN_PATTERN_2;
3640 if (IS_GEN6(dev)) {
3641 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3642 /* SNB-B */
3643 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3644 }
3645 I915_WRITE(reg, temp);
3646
3647 reg = FDI_RX_CTL(pipe);
3648 temp = I915_READ(reg);
3649 if (HAS_PCH_CPT(dev)) {
3650 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3651 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3652 } else {
3653 temp &= ~FDI_LINK_TRAIN_NONE;
3654 temp |= FDI_LINK_TRAIN_PATTERN_2;
3655 }
3656 I915_WRITE(reg, temp);
3657
3658 POSTING_READ(reg);
3659 udelay(150);
3660
3661 for (i = 0; i < 4; i++) {
3662 reg = FDI_TX_CTL(pipe);
3663 temp = I915_READ(reg);
3664 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3665 temp |= snb_b_fdi_train_param[i];
3666 I915_WRITE(reg, temp);
3667
3668 POSTING_READ(reg);
3669 udelay(500);
3670
3671 for (retry = 0; retry < 5; retry++) {
3672 reg = FDI_RX_IIR(pipe);
3673 temp = I915_READ(reg);
3674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3675 if (temp & FDI_RX_SYMBOL_LOCK) {
3676 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3677 DRM_DEBUG_KMS("FDI train 2 done.\n");
3678 break;
3679 }
3680 udelay(50);
3681 }
3682 if (retry < 5)
3683 break;
3684 }
3685 if (i == 4)
3686 DRM_ERROR("FDI train 2 fail!\n");
3687
3688 DRM_DEBUG_KMS("FDI train done.\n");
3689}
3690
3691/* Manual link training for Ivy Bridge A0 parts */
3692static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3693{
3694 struct drm_device *dev = crtc->dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697 int pipe = intel_crtc->pipe;
3698 u32 reg, temp, i, j;
3699
3700 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3701 for train result */
3702 reg = FDI_RX_IMR(pipe);
3703 temp = I915_READ(reg);
3704 temp &= ~FDI_RX_SYMBOL_LOCK;
3705 temp &= ~FDI_RX_BIT_LOCK;
3706 I915_WRITE(reg, temp);
3707
3708 POSTING_READ(reg);
3709 udelay(150);
3710
3711 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3712 I915_READ(FDI_RX_IIR(pipe)));
3713
3714 /* Try each vswing and preemphasis setting twice before moving on */
3715 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3716 /* disable first in case we need to retry */
3717 reg = FDI_TX_CTL(pipe);
3718 temp = I915_READ(reg);
3719 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3720 temp &= ~FDI_TX_ENABLE;
3721 I915_WRITE(reg, temp);
3722
3723 reg = FDI_RX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 temp &= ~FDI_LINK_TRAIN_AUTO;
3726 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3727 temp &= ~FDI_RX_ENABLE;
3728 I915_WRITE(reg, temp);
3729
3730 /* enable CPU FDI TX and PCH FDI RX */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3734 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3735 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3736 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3737 temp |= snb_b_fdi_train_param[j/2];
3738 temp |= FDI_COMPOSITE_SYNC;
3739 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3740
3741 I915_WRITE(FDI_RX_MISC(pipe),
3742 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3743
3744 reg = FDI_RX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3747 temp |= FDI_COMPOSITE_SYNC;
3748 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3749
3750 POSTING_READ(reg);
3751 udelay(1); /* should be 0.5us */
3752
3753 for (i = 0; i < 4; i++) {
3754 reg = FDI_RX_IIR(pipe);
3755 temp = I915_READ(reg);
3756 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3757
3758 if (temp & FDI_RX_BIT_LOCK ||
3759 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3760 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3761 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3762 i);
3763 break;
3764 }
3765 udelay(1); /* should be 0.5us */
3766 }
3767 if (i == 4) {
3768 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3769 continue;
3770 }
3771
3772 /* Train 2 */
3773 reg = FDI_TX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3776 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3777 I915_WRITE(reg, temp);
3778
3779 reg = FDI_RX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3782 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3783 I915_WRITE(reg, temp);
3784
3785 POSTING_READ(reg);
3786 udelay(2); /* should be 1.5us */
3787
3788 for (i = 0; i < 4; i++) {
3789 reg = FDI_RX_IIR(pipe);
3790 temp = I915_READ(reg);
3791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3792
3793 if (temp & FDI_RX_SYMBOL_LOCK ||
3794 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3795 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3796 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3797 i);
3798 goto train_done;
3799 }
3800 udelay(2); /* should be 1.5us */
3801 }
3802 if (i == 4)
3803 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3804 }
3805
3806train_done:
3807 DRM_DEBUG_KMS("FDI train done.\n");
3808}
3809
3810static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3811{
3812 struct drm_device *dev = intel_crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 int pipe = intel_crtc->pipe;
3815 u32 reg, temp;
3816
3817
3818 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3819 reg = FDI_RX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3822 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3823 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3824 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3825
3826 POSTING_READ(reg);
3827 udelay(200);
3828
3829 /* Switch from Rawclk to PCDclk */
3830 temp = I915_READ(reg);
3831 I915_WRITE(reg, temp | FDI_PCDCLK);
3832
3833 POSTING_READ(reg);
3834 udelay(200);
3835
3836 /* Enable CPU FDI TX PLL, always on for Ironlake */
3837 reg = FDI_TX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3840 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844 }
3845}
3846
3847static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3848{
3849 struct drm_device *dev = intel_crtc->base.dev;
3850 struct drm_i915_private *dev_priv = dev->dev_private;
3851 int pipe = intel_crtc->pipe;
3852 u32 reg, temp;
3853
3854 /* Switch from PCDclk to Rawclk */
3855 reg = FDI_RX_CTL(pipe);
3856 temp = I915_READ(reg);
3857 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3858
3859 /* Disable CPU FDI TX PLL */
3860 reg = FDI_TX_CTL(pipe);
3861 temp = I915_READ(reg);
3862 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3863
3864 POSTING_READ(reg);
3865 udelay(100);
3866
3867 reg = FDI_RX_CTL(pipe);
3868 temp = I915_READ(reg);
3869 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3870
3871 /* Wait for the clocks to turn off. */
3872 POSTING_READ(reg);
3873 udelay(100);
3874}
3875
3876static void ironlake_fdi_disable(struct drm_crtc *crtc)
3877{
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3881 int pipe = intel_crtc->pipe;
3882 u32 reg, temp;
3883
3884 /* disable CPU FDI tx and PCH FDI rx */
3885 reg = FDI_TX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3888 POSTING_READ(reg);
3889
3890 reg = FDI_RX_CTL(pipe);
3891 temp = I915_READ(reg);
3892 temp &= ~(0x7 << 16);
3893 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3894 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3895
3896 POSTING_READ(reg);
3897 udelay(100);
3898
3899 /* Ironlake workaround, disable clock pointer after downing FDI */
3900 if (HAS_PCH_IBX(dev))
3901 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3902
3903 /* still set train pattern 1 */
3904 reg = FDI_TX_CTL(pipe);
3905 temp = I915_READ(reg);
3906 temp &= ~FDI_LINK_TRAIN_NONE;
3907 temp |= FDI_LINK_TRAIN_PATTERN_1;
3908 I915_WRITE(reg, temp);
3909
3910 reg = FDI_RX_CTL(pipe);
3911 temp = I915_READ(reg);
3912 if (HAS_PCH_CPT(dev)) {
3913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3915 } else {
3916 temp &= ~FDI_LINK_TRAIN_NONE;
3917 temp |= FDI_LINK_TRAIN_PATTERN_1;
3918 }
3919 /* BPC in FDI rx is consistent with that in PIPECONF */
3920 temp &= ~(0x07 << 16);
3921 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3922 I915_WRITE(reg, temp);
3923
3924 POSTING_READ(reg);
3925 udelay(100);
3926}
3927
3928bool intel_has_pending_fb_unpin(struct drm_device *dev)
3929{
3930 struct intel_crtc *crtc;
3931
3932 /* Note that we don't need to be called with mode_config.lock here
3933 * as our list of CRTC objects is static for the lifetime of the
3934 * device and so cannot disappear as we iterate. Similarly, we can
3935 * happily treat the predicates as racy, atomic checks as userspace
3936 * cannot claim and pin a new fb without at least acquring the
3937 * struct_mutex and so serialising with us.
3938 */
3939 for_each_intel_crtc(dev, crtc) {
3940 if (atomic_read(&crtc->unpin_work_count) == 0)
3941 continue;
3942
3943 if (crtc->unpin_work)
3944 intel_wait_for_vblank(dev, crtc->pipe);
3945
3946 return true;
3947 }
3948
3949 return false;
3950}
3951
3952static void page_flip_completed(struct intel_crtc *intel_crtc)
3953{
3954 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3955 struct intel_unpin_work *work = intel_crtc->unpin_work;
3956
3957 /* ensure that the unpin work is consistent wrt ->pending. */
3958 smp_rmb();
3959 intel_crtc->unpin_work = NULL;
3960
3961 if (work->event)
3962 drm_send_vblank_event(intel_crtc->base.dev,
3963 intel_crtc->pipe,
3964 work->event);
3965
3966 drm_crtc_vblank_put(&intel_crtc->base);
3967
3968#ifdef __NetBSD__ /* XXX */
3969 {
3970 unsigned long flags;
3971 spin_lock_irqsave(&dev_priv->pending_flip_lock, flags);
3972 DRM_SPIN_WAKEUP_ALL(&dev_priv->pending_flip_queue,
3973 &dev_priv->pending_flip_lock);
3974 spin_unlock_irqrestore(&dev_priv->pending_flip_lock, flags);
3975 }
3976#else
3977 wake_up_all(&dev_priv->pending_flip_queue);
3978#endif
3979 trace_i915_flip_complete(intel_crtc->plane,
3980 work->pending_flip_obj);
3981
3982 queue_work(dev_priv->wq, &work->work);
3983}
3984
3985void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3986{
3987 struct drm_device *dev = crtc->dev;
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989
3990#ifdef __NetBSD__
3991 bool timedout;
3992 if (cold) {
3993 unsigned timo = 1000;
3994 timedout = false;
3995 while (intel_crtc_has_pending_flip(crtc)) {
3996 if (WARN_ON(timo-- == 0)) {
3997 /* Give up. */
3998 timedout = true;
3999 break;
4000 }
4001 DELAY(10);
4002 }
4003 } else {
4004 unsigned long flags;
4005 int ret;
4006
4007 spin_lock_irqsave(&dev_priv->pending_flip_lock, flags);
4008 WARN_ON(DRM_SPIN_WAITERS_P(&dev_priv->pending_flip_queue,
4009 &dev_priv->pending_flip_lock));
4010 DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret,
4011 &dev_priv->pending_flip_queue,
4012 &dev_priv->pending_flip_lock,
4013 60*HZ,
4014 !intel_crtc_has_pending_flip(crtc));
4015 spin_unlock_irqrestore(&dev_priv->pending_flip_lock, flags);
4016 timedout = (ret == 0);
4017 }
4018 if (timedout) {
4019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4020
4021 spin_lock_irq(&dev->event_lock);
4022 if (intel_crtc->unpin_work) {
4023 WARN_ONCE(1, "Removing stuck page flip\n");
4024 page_flip_completed(intel_crtc);
4025 }
4026 spin_unlock_irq(&dev->event_lock);
4027 }
4028#else
4029 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4030 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
4031 !intel_crtc_has_pending_flip(crtc),
4032 60*HZ) == 0)) {
4033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4034
4035 spin_lock_irq(&dev->event_lock);
4036 if (intel_crtc->unpin_work) {
4037 WARN_ONCE(1, "Removing stuck page flip\n");
4038 page_flip_completed(intel_crtc);
4039 }
4040 spin_unlock_irq(&dev->event_lock);
4041 }
4042#endif
4043
4044 if (crtc->primary->fb) {
4045 mutex_lock(&dev->struct_mutex);
4046 intel_finish_fb(crtc->primary->fb);
4047 mutex_unlock(&dev->struct_mutex);
4048 }
4049}
4050
4051/* Program iCLKIP clock to the desired frequency */
4052static void lpt_program_iclkip(struct drm_crtc *crtc)
4053{
4054 struct drm_device *dev = crtc->dev;
4055 struct drm_i915_private *dev_priv = dev->dev_private;
4056 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4057 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4058 u32 temp;
4059
4060 mutex_lock(&dev_priv->sb_lock);
4061
4062 /* It is necessary to ungate the pixclk gate prior to programming
4063 * the divisors, and gate it back when it is done.
4064 */
4065 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4066
4067 /* Disable SSCCTL */
4068 intel_sbi_write(dev_priv, SBI_SSCCTL6,
4069 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4070 SBI_SSCCTL_DISABLE,
4071 SBI_ICLK);
4072
4073 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
4074 if (clock == 20000) {
4075 auxdiv = 1;
4076 divsel = 0x41;
4077 phaseinc = 0x20;
4078 } else {
4079 /* The iCLK virtual clock root frequency is in MHz,
4080 * but the adjusted_mode->crtc_clock in in KHz. To get the
4081 * divisors, it is necessary to divide one by another, so we
4082 * convert the virtual clock precision to KHz here for higher
4083 * precision.
4084 */
4085 u32 iclk_virtual_root_freq = 172800 * 1000;
4086 u32 iclk_pi_range = 64;
4087 u32 desired_divisor, msb_divisor_value, pi_value;
4088
4089 desired_divisor = (iclk_virtual_root_freq / clock);
4090 msb_divisor_value = desired_divisor / iclk_pi_range;
4091 pi_value = desired_divisor % iclk_pi_range;
4092
4093 auxdiv = 0;
4094 divsel = msb_divisor_value - 2;
4095 phaseinc = pi_value;
4096 }
4097
4098 /* This should not happen with any sane values */
4099 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4100 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4101 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4102 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4103
4104 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4105 clock,
4106 auxdiv,
4107 divsel,
4108 phasedir,
4109 phaseinc);
4110
4111 /* Program SSCDIVINTPHASE6 */
4112 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4113 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4114 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4115 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4116 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4117 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4118 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4119 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4120
4121 /* Program SSCAUXDIV */
4122 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4123 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4124 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4125 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4126
4127 /* Enable modulator and associated divider */
4128 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4129 temp &= ~SBI_SSCCTL_DISABLE;
4130 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4131
4132 /* Wait for initialization time */
4133 udelay(24);
4134
4135 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4136
4137 mutex_unlock(&dev_priv->sb_lock);
4138}
4139
4140static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4141 enum i915_pipe pch_transcoder)
4142{
4143 struct drm_device *dev = crtc->base.dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4146
4147 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4148 I915_READ(HTOTAL(cpu_transcoder)));
4149 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4150 I915_READ(HBLANK(cpu_transcoder)));
4151 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4152 I915_READ(HSYNC(cpu_transcoder)));
4153
4154 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4155 I915_READ(VTOTAL(cpu_transcoder)));
4156 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4157 I915_READ(VBLANK(cpu_transcoder)));
4158 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4159 I915_READ(VSYNC(cpu_transcoder)));
4160 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4161 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4162}
4163
4164static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4165{
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 uint32_t temp;
4168
4169 temp = I915_READ(SOUTH_CHICKEN1);
4170 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4171 return;
4172
4173 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4174 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4175
4176 temp &= ~FDI_BC_BIFURCATION_SELECT;
4177 if (enable)
4178 temp |= FDI_BC_BIFURCATION_SELECT;
4179
4180 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4181 I915_WRITE(SOUTH_CHICKEN1, temp);
4182 POSTING_READ(SOUTH_CHICKEN1);
4183}
4184
4185static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4186{
4187 struct drm_device *dev = intel_crtc->base.dev;
4188
4189 switch (intel_crtc->pipe) {
4190 case PIPE_A:
4191 break;
4192 case PIPE_B:
4193 if (intel_crtc->config->fdi_lanes > 2)
4194 cpt_set_fdi_bc_bifurcation(dev, false);
4195 else
4196 cpt_set_fdi_bc_bifurcation(dev, true);
4197
4198 break;
4199 case PIPE_C:
4200 cpt_set_fdi_bc_bifurcation(dev, true);
4201
4202 break;
4203 default:
4204 BUG();
4205 }
4206}
4207
4208/*
4209 * Enable PCH resources required for PCH ports:
4210 * - PCH PLLs
4211 * - FDI training & RX/TX
4212 * - update transcoder timings
4213 * - DP transcoding bits
4214 * - transcoder
4215 */
4216static void ironlake_pch_enable(struct drm_crtc *crtc)
4217{
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4221 int pipe = intel_crtc->pipe;
4222 u32 reg, temp;
4223
4224 assert_pch_transcoder_disabled(dev_priv, pipe);
4225
4226 if (IS_IVYBRIDGE(dev))
4227 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4228
4229 /* Write the TU size bits before fdi link training, so that error
4230 * detection works. */
4231 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4232 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4233
4234 /* For PCH output, training FDI link */
4235 dev_priv->display.fdi_link_train(crtc);
4236
4237 /* We need to program the right clock selection before writing the pixel
4238 * mutliplier into the DPLL. */
4239 if (HAS_PCH_CPT(dev)) {
4240 u32 sel;
4241
4242 temp = I915_READ(PCH_DPLL_SEL);
4243 temp |= TRANS_DPLL_ENABLE(pipe);
4244 sel = TRANS_DPLLB_SEL(pipe);
4245 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4246 temp |= sel;
4247 else
4248 temp &= ~sel;
4249 I915_WRITE(PCH_DPLL_SEL, temp);
4250 }
4251
4252 /* XXX: pch pll's can be enabled any time before we enable the PCH
4253 * transcoder, and we actually should do this to not upset any PCH
4254 * transcoder that already use the clock when we share it.
4255 *
4256 * Note that enable_shared_dpll tries to do the right thing, but
4257 * get_shared_dpll unconditionally resets the pll - we need that to have
4258 * the right LVDS enable sequence. */
4259 intel_enable_shared_dpll(intel_crtc);
4260
4261 /* set transcoder timing, panel must allow it */
4262 assert_panel_unlocked(dev_priv, pipe);
4263 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4264
4265 intel_fdi_normal_train(crtc);
4266
4267 /* For PCH DP, enable TRANS_DP_CTL */
4268 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4269 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4270 reg = TRANS_DP_CTL(pipe);
4271 temp = I915_READ(reg);
4272 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4273 TRANS_DP_SYNC_MASK |
4274 TRANS_DP_BPC_MASK);
4275 temp |= TRANS_DP_OUTPUT_ENABLE;
4276 temp |= bpc << 9; /* same format but at 11:9 */
4277
4278 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4279 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4280 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4281 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4282
4283 switch (intel_trans_dp_port_sel(crtc)) {
4284 case PCH_DP_B:
4285 temp |= TRANS_DP_PORT_SEL_B;
4286 break;
4287 case PCH_DP_C:
4288 temp |= TRANS_DP_PORT_SEL_C;
4289 break;
4290 case PCH_DP_D:
4291 temp |= TRANS_DP_PORT_SEL_D;
4292 break;
4293 default:
4294 BUG();
4295 }
4296
4297 I915_WRITE(reg, temp);
4298 }
4299
4300 ironlake_enable_pch_transcoder(dev_priv, pipe);
4301}
4302
4303static void lpt_pch_enable(struct drm_crtc *crtc)
4304{
4305 struct drm_device *dev = crtc->dev;
4306 struct drm_i915_private *dev_priv = dev->dev_private;
4307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4308 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4309
4310 assert_pch_transcoder_disabled(dev_priv, (enum i915_pipe) TRANSCODER_A);
4311
4312 lpt_program_iclkip(crtc);
4313
4314 /* Set transcoder timing. */
4315 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4316
4317 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4318}
4319
4320struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4321 struct intel_crtc_state *crtc_state)
4322{
4323 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4324 struct intel_shared_dpll *pll;
4325 struct intel_shared_dpll_config *shared_dpll;
4326 enum intel_dpll_id i;
4327 int max = dev_priv->num_shared_dpll;
4328
4329 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4330
4331 if (HAS_PCH_IBX(dev_priv->dev)) {
4332 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4333 i = (enum intel_dpll_id) crtc->pipe;
4334 pll = &dev_priv->shared_dplls[i];
4335
4336 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4337 crtc->base.base.id, pll->name);
4338
4339 WARN_ON(shared_dpll[i].crtc_mask);
4340
4341 goto found;
4342 }
4343
4344 if (IS_BROXTON(dev_priv->dev)) {
4345 /* PLL is attached to port in bxt */
4346 struct intel_encoder *encoder;
4347 struct intel_digital_port *intel_dig_port;
4348
4349 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4350 if (WARN_ON(!encoder))
4351 return NULL;
4352
4353 intel_dig_port = enc_to_dig_port(&encoder->base);
4354 /* 1:1 mapping between ports and PLLs */
4355 i = (enum intel_dpll_id)intel_dig_port->port;
4356 pll = &dev_priv->shared_dplls[i];
4357 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4358 crtc->base.base.id, pll->name);
4359 WARN_ON(shared_dpll[i].crtc_mask);
4360
4361 goto found;
4362 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4363 /* Do not consider SPLL */
4364 max = 2;
4365
4366 for (i = 0; i < max; i++) {
4367 pll = &dev_priv->shared_dplls[i];
4368
4369 /* Only want to check enabled timings first */
4370 if (shared_dpll[i].crtc_mask == 0)
4371 continue;
4372
4373 if (memcmp(&crtc_state->dpll_hw_state,
4374 &shared_dpll[i].hw_state,
4375 sizeof(crtc_state->dpll_hw_state)) == 0) {
4376 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4377 crtc->base.base.id, pll->name,
4378 shared_dpll[i].crtc_mask,
4379 pll->active);
4380 goto found;
4381 }
4382 }
4383
4384 /* Ok no matching timings, maybe there's a free one? */
4385 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4386 pll = &dev_priv->shared_dplls[i];
4387 if (shared_dpll[i].crtc_mask == 0) {
4388 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4389 crtc->base.base.id, pll->name);
4390 goto found;
4391 }
4392 }
4393
4394 return NULL;
4395
4396found:
4397 if (shared_dpll[i].crtc_mask == 0)
4398 shared_dpll[i].hw_state =
4399 crtc_state->dpll_hw_state;
4400
4401 crtc_state->shared_dpll = i;
4402 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4403 pipe_name(crtc->pipe));
4404
4405 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4406
4407 return pll;
4408}
4409
4410static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4411{
4412 struct drm_i915_private *dev_priv = to_i915(state->dev);
4413 struct intel_shared_dpll_config *shared_dpll;
4414 struct intel_shared_dpll *pll;
4415 enum intel_dpll_id i;
4416
4417 if (!to_intel_atomic_state(state)->dpll_set)
4418 return;
4419
4420 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4421 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4422 pll = &dev_priv->shared_dplls[i];
4423 pll->config = shared_dpll[i];
4424 }
4425}
4426
4427static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4428{
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430 int dslreg = PIPEDSL(pipe);
4431 u32 temp;
4432
4433 temp = I915_READ(dslreg);
4434 udelay(500);
4435 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4436 if (wait_for(I915_READ(dslreg) != temp, 5))
4437 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4438 }
4439}
4440
4441static int
4442skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4443 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4444 int src_w, int src_h, int dst_w, int dst_h)
4445{
4446 struct intel_crtc_scaler_state *scaler_state =
4447 &crtc_state->scaler_state;
4448 struct intel_crtc *intel_crtc =
4449 to_intel_crtc(crtc_state->base.crtc);
4450 int need_scaling;
4451
4452 need_scaling = intel_rotation_90_or_270(rotation) ?
4453 (src_h != dst_w || src_w != dst_h):
4454 (src_w != dst_w || src_h != dst_h);
4455
4456 /*
4457 * if plane is being disabled or scaler is no more required or force detach
4458 * - free scaler binded to this plane/crtc
4459 * - in order to do this, update crtc->scaler_usage
4460 *
4461 * Here scaler state in crtc_state is set free so that
4462 * scaler can be assigned to other user. Actual register
4463 * update to free the scaler is done in plane/panel-fit programming.
4464 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4465 */
4466 if (force_detach || !need_scaling) {
4467 if (*scaler_id >= 0) {
4468 scaler_state->scaler_users &= ~(1 << scaler_user);
4469 scaler_state->scalers[*scaler_id].in_use = 0;
4470
4471 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4472 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4473 intel_crtc->pipe, scaler_user, *scaler_id,
4474 scaler_state->scaler_users);
4475 *scaler_id = -1;
4476 }
4477 return 0;
4478 }
4479
4480 /* range checks */
4481 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4482 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4483
4484 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4485 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4486 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4487 "size is out of scaler range\n",
4488 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4489 return -EINVAL;
4490 }
4491
4492 /* mark this plane as a scaler user in crtc_state */
4493 scaler_state->scaler_users |= (1 << scaler_user);
4494 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4495 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4496 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4497 scaler_state->scaler_users);
4498
4499 return 0;
4500}
4501
4502/**
4503 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4504 *
4505 * @state: crtc's scaler state
4506 *
4507 * Return
4508 * 0 - scaler_usage updated successfully
4509 * error - requested scaling cannot be supported or other error condition
4510 */
4511int skl_update_scaler_crtc(struct intel_crtc_state *state)
4512{
4513 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4514 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4515
4516 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4517 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4518
4519 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4520 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4521 state->pipe_src_w, state->pipe_src_h,
4522 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4523}
4524
4525/**
4526 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4527 *
4528 * @state: crtc's scaler state
4529 * @plane_state: atomic plane state to update
4530 *
4531 * Return
4532 * 0 - scaler_usage updated successfully
4533 * error - requested scaling cannot be supported or other error condition
4534 */
4535static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4536 struct intel_plane_state *plane_state)
4537{
4538
4539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4540 struct intel_plane *intel_plane =
4541 to_intel_plane(plane_state->base.plane);
4542 struct drm_framebuffer *fb = plane_state->base.fb;
4543 int ret;
4544
4545 bool force_detach = !fb || !plane_state->visible;
4546
4547 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4548 intel_plane->base.base.id, intel_crtc->pipe,
4549 drm_plane_index(&intel_plane->base));
4550
4551 ret = skl_update_scaler(crtc_state, force_detach,
4552 drm_plane_index(&intel_plane->base),
4553 &plane_state->scaler_id,
4554 plane_state->base.rotation,
4555 drm_rect_width(&plane_state->src) >> 16,
4556 drm_rect_height(&plane_state->src) >> 16,
4557 drm_rect_width(&plane_state->dst),
4558 drm_rect_height(&plane_state->dst));
4559
4560 if (ret || plane_state->scaler_id < 0)
4561 return ret;
4562
4563 /* check colorkey */
4564 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4565 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4566 intel_plane->base.base.id);
4567 return -EINVAL;
4568 }
4569
4570 /* Check src format */
4571 switch (fb->pixel_format) {
4572 case DRM_FORMAT_RGB565:
4573 case DRM_FORMAT_XBGR8888:
4574 case DRM_FORMAT_XRGB8888:
4575 case DRM_FORMAT_ABGR8888:
4576 case DRM_FORMAT_ARGB8888:
4577 case DRM_FORMAT_XRGB2101010:
4578 case DRM_FORMAT_XBGR2101010:
4579 case DRM_FORMAT_YUYV:
4580 case DRM_FORMAT_YVYU:
4581 case DRM_FORMAT_UYVY:
4582 case DRM_FORMAT_VYUY:
4583 break;
4584 default:
4585 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4586 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4587 return -EINVAL;
4588 }
4589
4590 return 0;
4591}
4592
4593static void skylake_scaler_disable(struct intel_crtc *crtc)
4594{
4595 int i;
4596
4597 for (i = 0; i < crtc->num_scalers; i++)
4598 skl_detach_scaler(crtc, i);
4599}
4600
4601static void skylake_pfit_enable(struct intel_crtc *crtc)
4602{
4603 struct drm_device *dev = crtc->base.dev;
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4605 int pipe = crtc->pipe;
4606 struct intel_crtc_scaler_state *scaler_state =
4607 &crtc->config->scaler_state;
4608
4609 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4610
4611 if (crtc->config->pch_pfit.enabled) {
4612 int id;
4613
4614 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4615 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4616 return;
4617 }
4618
4619 id = scaler_state->scaler_id;
4620 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4621 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4622 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4623 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4624
4625 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4626 }
4627}
4628
4629static void ironlake_pfit_enable(struct intel_crtc *crtc)
4630{
4631 struct drm_device *dev = crtc->base.dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633 int pipe = crtc->pipe;
4634
4635 if (crtc->config->pch_pfit.enabled) {
4636 /* Force use of hard-coded filter coefficients
4637 * as some pre-programmed values are broken,
4638 * e.g. x201.
4639 */
4640 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4641 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4642 PF_PIPE_SEL_IVB(pipe));
4643 else
4644 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4645 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4646 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4647 }
4648}
4649
4650void hsw_enable_ips(struct intel_crtc *crtc)
4651{
4652 struct drm_device *dev = crtc->base.dev;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654
4655 if (!crtc->config->ips_enabled)
4656 return;
4657
4658 /* We can only enable IPS after we enable a plane and wait for a vblank */
4659 intel_wait_for_vblank(dev, crtc->pipe);
4660
4661 assert_plane_enabled(dev_priv, crtc->plane);
4662 if (IS_BROADWELL(dev)) {
4663 mutex_lock(&dev_priv->rps.hw_lock);
4664 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4665 mutex_unlock(&dev_priv->rps.hw_lock);
4666 /* Quoting Art Runyan: "its not safe to expect any particular
4667 * value in IPS_CTL bit 31 after enabling IPS through the
4668 * mailbox." Moreover, the mailbox may return a bogus state,
4669 * so we need to just enable it and continue on.
4670 */
4671 } else {
4672 I915_WRITE(IPS_CTL, IPS_ENABLE);
4673 /* The bit only becomes 1 in the next vblank, so this wait here
4674 * is essentially intel_wait_for_vblank. If we don't have this
4675 * and don't wait for vblanks until the end of crtc_enable, then
4676 * the HW state readout code will complain that the expected
4677 * IPS_CTL value is not the one we read. */
4678 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4679 DRM_ERROR("Timed out waiting for IPS enable\n");
4680 }
4681}
4682
4683void hsw_disable_ips(struct intel_crtc *crtc)
4684{
4685 struct drm_device *dev = crtc->base.dev;
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687
4688 if (!crtc->config->ips_enabled)
4689 return;
4690
4691 assert_plane_enabled(dev_priv, crtc->plane);
4692 if (IS_BROADWELL(dev)) {
4693 mutex_lock(&dev_priv->rps.hw_lock);
4694 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4695 mutex_unlock(&dev_priv->rps.hw_lock);
4696 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4697 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4698 DRM_ERROR("Timed out waiting for IPS disable\n");
4699 } else {
4700 I915_WRITE(IPS_CTL, 0);
4701 POSTING_READ(IPS_CTL);
4702 }
4703
4704 /* We need to wait for a vblank before we can disable the plane. */
4705 intel_wait_for_vblank(dev, crtc->pipe);
4706}
4707
4708/** Loads the palette/gamma unit for the CRTC with the prepared values */
4709static void intel_crtc_load_lut(struct drm_crtc *crtc)
4710{
4711 struct drm_device *dev = crtc->dev;
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4714 enum i915_pipe pipe = intel_crtc->pipe;
4715 int i;
4716 bool reenable_ips = false;
4717
4718 /* The clocks have to be on to load the palette. */
4719 if (!crtc->state->active)
4720 return;
4721
4722 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4723 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4724 assert_dsi_pll_enabled(dev_priv);
4725 else
4726 assert_pll_enabled(dev_priv, pipe);
4727 }
4728
4729 /* Workaround : Do not read or write the pipe palette/gamma data while
4730 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4731 */
4732 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4733 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4734 GAMMA_MODE_MODE_SPLIT)) {
4735 hsw_disable_ips(intel_crtc);
4736 reenable_ips = true;
4737 }
4738
4739 for (i = 0; i < 256; i++) {
4740 u32 palreg;
4741
4742 if (HAS_GMCH_DISPLAY(dev))
4743 palreg = PALETTE(pipe, i);
4744 else
4745 palreg = LGC_PALETTE(pipe, i);
4746
4747 I915_WRITE(palreg,
4748 (intel_crtc->lut_r[i] << 16) |
4749 (intel_crtc->lut_g[i] << 8) |
4750 intel_crtc->lut_b[i]);
4751 }
4752
4753 if (reenable_ips)
4754 hsw_enable_ips(intel_crtc);
4755}
4756
4757static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4758{
4759 if (intel_crtc->overlay) {
4760 struct drm_device *dev = intel_crtc->base.dev;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762
4763 mutex_lock(&dev->struct_mutex);
4764 dev_priv->mm.interruptible = false;
4765 (void) intel_overlay_switch_off(intel_crtc->overlay);
4766 dev_priv->mm.interruptible = true;
4767 mutex_unlock(&dev->struct_mutex);
4768 }
4769
4770 /* Let userspace switch the overlay on again. In most cases userspace
4771 * has to recompute where to put it anyway.
4772 */
4773}
4774
4775/**
4776 * intel_post_enable_primary - Perform operations after enabling primary plane
4777 * @crtc: the CRTC whose primary plane was just enabled
4778 *
4779 * Performs potentially sleeping operations that must be done after the primary
4780 * plane is enabled, such as updating FBC and IPS. Note that this may be
4781 * called due to an explicit primary plane update, or due to an implicit
4782 * re-enable that is caused when a sprite plane is updated to no longer
4783 * completely hide the primary plane.
4784 */
4785static void
4786intel_post_enable_primary(struct drm_crtc *crtc)
4787{
4788 struct drm_device *dev = crtc->dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4791 int pipe = intel_crtc->pipe;
4792
4793 /*
4794 * BDW signals flip done immediately if the plane
4795 * is disabled, even if the plane enable is already
4796 * armed to occur at the next vblank :(
4797 */
4798 if (IS_BROADWELL(dev))
4799 intel_wait_for_vblank(dev, pipe);
4800
4801 /*
4802 * FIXME IPS should be fine as long as one plane is
4803 * enabled, but in practice it seems to have problems
4804 * when going from primary only to sprite only and vice
4805 * versa.
4806 */
4807 hsw_enable_ips(intel_crtc);
4808
4809 /*
4810 * Gen2 reports pipe underruns whenever all planes are disabled.
4811 * So don't enable underrun reporting before at least some planes
4812 * are enabled.
4813 * FIXME: Need to fix the logic to work when we turn off all planes
4814 * but leave the pipe running.
4815 */
4816 if (IS_GEN2(dev))
4817 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4818
4819 /* Underruns don't raise interrupts, so check manually. */
4820 if (HAS_GMCH_DISPLAY(dev))
4821 i9xx_check_fifo_underruns(dev_priv);
4822}
4823
4824/**
4825 * intel_pre_disable_primary - Perform operations before disabling primary plane
4826 * @crtc: the CRTC whose primary plane is to be disabled
4827 *
4828 * Performs potentially sleeping operations that must be done before the
4829 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4830 * be called due to an explicit primary plane update, or due to an implicit
4831 * disable that is caused when a sprite plane completely hides the primary
4832 * plane.
4833 */
4834static void
4835intel_pre_disable_primary(struct drm_crtc *crtc)
4836{
4837 struct drm_device *dev = crtc->dev;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4840 int pipe = intel_crtc->pipe;
4841
4842 /*
4843 * Gen2 reports pipe underruns whenever all planes are disabled.
4844 * So diasble underrun reporting before all the planes get disabled.
4845 * FIXME: Need to fix the logic to work when we turn off all planes
4846 * but leave the pipe running.
4847 */
4848 if (IS_GEN2(dev))
4849 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4850
4851 /*
4852 * Vblank time updates from the shadow to live plane control register
4853 * are blocked if the memory self-refresh mode is active at that
4854 * moment. So to make sure the plane gets truly disabled, disable
4855 * first the self-refresh mode. The self-refresh enable bit in turn
4856 * will be checked/applied by the HW only at the next frame start
4857 * event which is after the vblank start event, so we need to have a
4858 * wait-for-vblank between disabling the plane and the pipe.
4859 */
4860 if (HAS_GMCH_DISPLAY(dev)) {
4861 intel_set_memory_cxsr(dev_priv, false);
4862 dev_priv->wm.vlv.cxsr = false;
4863 intel_wait_for_vblank(dev, pipe);
4864 }
4865
4866 /*
4867 * FIXME IPS should be fine as long as one plane is
4868 * enabled, but in practice it seems to have problems
4869 * when going from primary only to sprite only and vice
4870 * versa.
4871 */
4872 hsw_disable_ips(intel_crtc);
4873}
4874
4875static void intel_post_plane_update(struct intel_crtc *crtc)
4876{
4877 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4878 struct drm_device *dev = crtc->base.dev;
4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880 struct drm_plane *plane;
4881
4882 if (atomic->wait_vblank)
4883 intel_wait_for_vblank(dev, crtc->pipe);
4884
4885 intel_frontbuffer_flip(dev, atomic->fb_bits);
4886
4887 if (atomic->disable_cxsr)
4888 crtc->wm.cxsr_allowed = true;
4889
4890 if (crtc->atomic.update_wm_post)
4891 intel_update_watermarks(&crtc->base);
4892
4893 if (atomic->update_fbc)
4894 intel_fbc_update(dev_priv);
4895
4896 if (atomic->post_enable_primary)
4897 intel_post_enable_primary(&crtc->base);
4898
4899 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4900 intel_update_sprite_watermarks(plane, &crtc->base,
4901 0, 0, 0, false, false);
4902
4903 memset(atomic, 0, sizeof(*atomic));
4904}
4905
4906static void intel_pre_plane_update(struct intel_crtc *crtc)
4907{
4908 struct drm_device *dev = crtc->base.dev;
4909 struct drm_i915_private *dev_priv = dev->dev_private;
4910 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4911 struct drm_plane *p;
4912
4913 /* Track fb's for any planes being disabled */
4914 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4915 struct intel_plane *plane = to_intel_plane(p);
4916
4917 mutex_lock(&dev->struct_mutex);
4918 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4919 plane->frontbuffer_bit);
4920 mutex_unlock(&dev->struct_mutex);
4921 }
4922
4923 if (atomic->wait_for_flips)
4924 intel_crtc_wait_for_pending_flips(&crtc->base);
4925
4926 if (atomic->disable_fbc)
4927 intel_fbc_disable_crtc(crtc);
4928
4929 if (crtc->atomic.disable_ips)
4930 hsw_disable_ips(crtc);
4931
4932 if (atomic->pre_disable_primary)
4933 intel_pre_disable_primary(&crtc->base);
4934
4935 if (atomic->disable_cxsr) {
4936 crtc->wm.cxsr_allowed = false;
4937 intel_set_memory_cxsr(dev_priv, false);
4938 }
4939}
4940
4941static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4942{
4943 struct drm_device *dev = crtc->dev;
4944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945 struct drm_plane *p;
4946 int pipe = intel_crtc->pipe;
4947
4948 intel_crtc_dpms_overlay_disable(intel_crtc);
4949
4950 drm_for_each_plane_mask(p, dev, plane_mask)
4951 to_intel_plane(p)->disable_plane(p, crtc);
4952
4953 /*
4954 * FIXME: Once we grow proper nuclear flip support out of this we need
4955 * to compute the mask of flip planes precisely. For the time being
4956 * consider this a flip to a NULL plane.
4957 */
4958 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4959}
4960
4961static void ironlake_crtc_enable(struct drm_crtc *crtc)
4962{
4963 struct drm_device *dev = crtc->dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966 struct intel_encoder *encoder;
4967 int pipe = intel_crtc->pipe;
4968
4969 if (WARN_ON(intel_crtc->active))
4970 return;
4971
4972 if (intel_crtc->config->has_pch_encoder)
4973 intel_prepare_shared_dpll(intel_crtc);
4974
4975 if (intel_crtc->config->has_dp_encoder)
4976 intel_dp_set_m_n(intel_crtc, M1_N1);
4977
4978 intel_set_pipe_timings(intel_crtc);
4979
4980 if (intel_crtc->config->has_pch_encoder) {
4981 intel_cpu_transcoder_set_m_n(intel_crtc,
4982 &intel_crtc->config->fdi_m_n, NULL);
4983 }
4984
4985 ironlake_set_pipeconf(crtc);
4986
4987 intel_crtc->active = true;
4988
4989 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4990 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4991
4992 for_each_encoder_on_crtc(dev, crtc, encoder)
4993 if (encoder->pre_enable)
4994 encoder->pre_enable(encoder);
4995
4996 if (intel_crtc->config->has_pch_encoder) {
4997 /* Note: FDI PLL enabling _must_ be done before we enable the
4998 * cpu pipes, hence this is separate from all the other fdi/pch
4999 * enabling. */
5000 ironlake_fdi_pll_enable(intel_crtc);
5001 } else {
5002 assert_fdi_tx_disabled(dev_priv, pipe);
5003 assert_fdi_rx_disabled(dev_priv, pipe);
5004 }
5005
5006 ironlake_pfit_enable(intel_crtc);
5007
5008 /*
5009 * On ILK+ LUT must be loaded before the pipe is running but with
5010 * clocks enabled
5011 */
5012 intel_crtc_load_lut(crtc);
5013
5014 intel_update_watermarks(crtc);
5015 intel_enable_pipe(intel_crtc);
5016
5017 if (intel_crtc->config->has_pch_encoder)
5018 ironlake_pch_enable(crtc);
5019
5020 assert_vblank_disabled(crtc);
5021 drm_crtc_vblank_on(crtc);
5022
5023 for_each_encoder_on_crtc(dev, crtc, encoder)
5024 encoder->enable(encoder);
5025
5026 if (HAS_PCH_CPT(dev))
5027 cpt_verify_modeset(dev, intel_crtc->pipe);
5028}
5029
5030/* IPS only exists on ULT machines and is tied to pipe A. */
5031static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5032{
5033 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5034}
5035
5036static void haswell_crtc_enable(struct drm_crtc *crtc)
5037{
5038 struct drm_device *dev = crtc->dev;
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5041 struct intel_encoder *encoder;
5042 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5043 struct intel_crtc_state *pipe_config =
5044 to_intel_crtc_state(crtc->state);
5045 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5046
5047 if (WARN_ON(intel_crtc->active))
5048 return;
5049
5050 if (intel_crtc_to_shared_dpll(intel_crtc))
5051 intel_enable_shared_dpll(intel_crtc);
5052
5053 if (intel_crtc->config->has_dp_encoder)
5054 intel_dp_set_m_n(intel_crtc, M1_N1);
5055
5056 intel_set_pipe_timings(intel_crtc);
5057
5058 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5059 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5060 intel_crtc->config->pixel_multiplier - 1);
5061 }
5062
5063 if (intel_crtc->config->has_pch_encoder) {
5064 intel_cpu_transcoder_set_m_n(intel_crtc,
5065 &intel_crtc->config->fdi_m_n, NULL);
5066 }
5067
5068 haswell_set_pipeconf(crtc);
5069
5070 intel_set_pipe_csc(crtc);
5071
5072 intel_crtc->active = true;
5073
5074 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5075 for_each_encoder_on_crtc(dev, crtc, encoder) {
5076 if (encoder->pre_pll_enable)
5077 encoder->pre_pll_enable(encoder);
5078 if (encoder->pre_enable)
5079 encoder->pre_enable(encoder);
5080 }
5081
5082 if (intel_crtc->config->has_pch_encoder) {
5083 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5084 true);
5085 dev_priv->display.fdi_link_train(crtc);
5086 }
5087
5088 if (!is_dsi)
5089 intel_ddi_enable_pipe_clock(intel_crtc);
5090
5091 if (INTEL_INFO(dev)->gen >= 9)
5092 skylake_pfit_enable(intel_crtc);
5093 else
5094 ironlake_pfit_enable(intel_crtc);
5095
5096 /*
5097 * On ILK+ LUT must be loaded before the pipe is running but with
5098 * clocks enabled
5099 */
5100 intel_crtc_load_lut(crtc);
5101
5102 intel_ddi_set_pipe_settings(crtc);
5103 if (!is_dsi)
5104 intel_ddi_enable_transcoder_func(crtc);
5105
5106 intel_update_watermarks(crtc);
5107 intel_enable_pipe(intel_crtc);
5108
5109 if (intel_crtc->config->has_pch_encoder)
5110 lpt_pch_enable(crtc);
5111
5112 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5113 intel_ddi_set_vc_payload_alloc(crtc, true);
5114
5115 assert_vblank_disabled(crtc);
5116 drm_crtc_vblank_on(crtc);
5117
5118 for_each_encoder_on_crtc(dev, crtc, encoder) {
5119 encoder->enable(encoder);
5120 intel_opregion_notify_encoder(encoder, true);
5121 }
5122
5123 /* If we change the relative order between pipe/planes enabling, we need
5124 * to change the workaround. */
5125 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5126 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5127 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5128 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5129 }
5130}
5131
5132static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5133{
5134 struct drm_device *dev = crtc->base.dev;
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5136 int pipe = crtc->pipe;
5137
5138 /* To avoid upsetting the power well on haswell only disable the pfit if
5139 * it's in use. The hw state code will make sure we get this right. */
5140 if (force || crtc->config->pch_pfit.enabled) {
5141 I915_WRITE(PF_CTL(pipe), 0);
5142 I915_WRITE(PF_WIN_POS(pipe), 0);
5143 I915_WRITE(PF_WIN_SZ(pipe), 0);
5144 }
5145}
5146
5147static void ironlake_crtc_disable(struct drm_crtc *crtc)
5148{
5149 struct drm_device *dev = crtc->dev;
5150 struct drm_i915_private *dev_priv = dev->dev_private;
5151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5152 struct intel_encoder *encoder;
5153 int pipe = intel_crtc->pipe;
5154 u32 reg, temp;
5155
5156 for_each_encoder_on_crtc(dev, crtc, encoder)
5157 encoder->disable(encoder);
5158
5159 drm_crtc_vblank_off(crtc);
5160 assert_vblank_disabled(crtc);
5161
5162 if (intel_crtc->config->has_pch_encoder)
5163 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5164
5165 intel_disable_pipe(intel_crtc);
5166
5167 ironlake_pfit_disable(intel_crtc, false);
5168
5169 if (intel_crtc->config->has_pch_encoder)
5170 ironlake_fdi_disable(crtc);
5171
5172 for_each_encoder_on_crtc(dev, crtc, encoder)
5173 if (encoder->post_disable)
5174 encoder->post_disable(encoder);
5175
5176 if (intel_crtc->config->has_pch_encoder) {
5177 ironlake_disable_pch_transcoder(dev_priv, pipe);
5178
5179 if (HAS_PCH_CPT(dev)) {
5180 /* disable TRANS_DP_CTL */
5181 reg = TRANS_DP_CTL(pipe);
5182 temp = I915_READ(reg);
5183 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5184 TRANS_DP_PORT_SEL_MASK);
5185 temp |= TRANS_DP_PORT_SEL_NONE;
5186 I915_WRITE(reg, temp);
5187
5188 /* disable DPLL_SEL */
5189 temp = I915_READ(PCH_DPLL_SEL);
5190 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5191 I915_WRITE(PCH_DPLL_SEL, temp);
5192 }
5193
5194 ironlake_fdi_pll_disable(intel_crtc);
5195 }
5196}
5197
5198static void haswell_crtc_disable(struct drm_crtc *crtc)
5199{
5200 struct drm_device *dev = crtc->dev;
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203 struct intel_encoder *encoder;
5204 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5205 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5206
5207 for_each_encoder_on_crtc(dev, crtc, encoder) {
5208 intel_opregion_notify_encoder(encoder, false);
5209 encoder->disable(encoder);
5210 }
5211
5212 drm_crtc_vblank_off(crtc);
5213 assert_vblank_disabled(crtc);
5214
5215 if (intel_crtc->config->has_pch_encoder)
5216 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5217 false);
5218 intel_disable_pipe(intel_crtc);
5219
5220 if (intel_crtc->config->dp_encoder_is_mst)
5221 intel_ddi_set_vc_payload_alloc(crtc, false);
5222
5223 if (!is_dsi)
5224 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5225
5226 if (INTEL_INFO(dev)->gen >= 9)
5227 skylake_scaler_disable(intel_crtc);
5228 else
5229 ironlake_pfit_disable(intel_crtc, false);
5230
5231 if (!is_dsi)
5232 intel_ddi_disable_pipe_clock(intel_crtc);
5233
5234 if (intel_crtc->config->has_pch_encoder) {
5235 lpt_disable_pch_transcoder(dev_priv);
5236 intel_ddi_fdi_disable(crtc);
5237 }
5238
5239 for_each_encoder_on_crtc(dev, crtc, encoder)
5240 if (encoder->post_disable)
5241 encoder->post_disable(encoder);
5242}
5243
5244static void i9xx_pfit_enable(struct intel_crtc *crtc)
5245{
5246 struct drm_device *dev = crtc->base.dev;
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 struct intel_crtc_state *pipe_config = crtc->config;
5249
5250 if (!pipe_config->gmch_pfit.control)
5251 return;
5252
5253 /*
5254 * The panel fitter should only be adjusted whilst the pipe is disabled,
5255 * according to register description and PRM.
5256 */
5257 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5258 assert_pipe_disabled(dev_priv, crtc->pipe);
5259
5260 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5261 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5262
5263 /* Border color in case we don't scale up to the full screen. Black by
5264 * default, change to something else for debugging. */
5265 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5266}
5267
5268static enum intel_display_power_domain port_to_power_domain(enum port port)
5269{
5270 switch (port) {
5271 case PORT_A:
5272 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5273 case PORT_B:
5274 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5275 case PORT_C:
5276 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5277 case PORT_D:
5278 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5279 case PORT_E:
5280 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5281 default:
5282 MISSING_CASE(port);
5283 return POWER_DOMAIN_PORT_OTHER;
5284 }
5285}
5286
5287static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5288{
5289 switch (port) {
5290 case PORT_A:
5291 return POWER_DOMAIN_AUX_A;
5292 case PORT_B:
5293 return POWER_DOMAIN_AUX_B;
5294 case PORT_C:
5295 return POWER_DOMAIN_AUX_C;
5296 case PORT_D:
5297 return POWER_DOMAIN_AUX_D;
5298 case PORT_E:
5299 /* FIXME: Check VBT for actual wiring of PORT E */
5300 return POWER_DOMAIN_AUX_D;
5301 default:
5302 MISSING_CASE(port);
5303 return POWER_DOMAIN_AUX_A;
5304 }
5305}
5306
5307#define for_each_power_domain(domain, mask) \
5308 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5309 if ((1 << (domain)) & (mask))
5310
5311enum intel_display_power_domain
5312intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5313{
5314 struct drm_device *dev = intel_encoder->base.dev;
5315 struct intel_digital_port *intel_dig_port;
5316
5317 switch (intel_encoder->type) {
5318 case INTEL_OUTPUT_UNKNOWN:
5319 /* Only DDI platforms should ever use this output type */
5320 WARN_ON_ONCE(!HAS_DDI(dev));
5321 case INTEL_OUTPUT_DISPLAYPORT:
5322 case INTEL_OUTPUT_HDMI:
5323 case INTEL_OUTPUT_EDP:
5324 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5325 return port_to_power_domain(intel_dig_port->port);
5326 case INTEL_OUTPUT_DP_MST:
5327 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5328 return port_to_power_domain(intel_dig_port->port);
5329 case INTEL_OUTPUT_ANALOG:
5330 return POWER_DOMAIN_PORT_CRT;
5331 case INTEL_OUTPUT_DSI:
5332 return POWER_DOMAIN_PORT_DSI;
5333 default:
5334 return POWER_DOMAIN_PORT_OTHER;
5335 }
5336}
5337
5338enum intel_display_power_domain
5339intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5340{
5341 struct drm_device *dev = intel_encoder->base.dev;
5342 struct intel_digital_port *intel_dig_port;
5343
5344 switch (intel_encoder->type) {
5345 case INTEL_OUTPUT_UNKNOWN:
5346 case INTEL_OUTPUT_HDMI:
5347 /*
5348 * Only DDI platforms should ever use these output types.
5349 * We can get here after the HDMI detect code has already set
5350 * the type of the shared encoder. Since we can't be sure
5351 * what's the status of the given connectors, play safe and
5352 * run the DP detection too.
5353 */
5354 WARN_ON_ONCE(!HAS_DDI(dev));
5355 case INTEL_OUTPUT_DISPLAYPORT:
5356 case INTEL_OUTPUT_EDP:
5357 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5358 return port_to_aux_power_domain(intel_dig_port->port);
5359 case INTEL_OUTPUT_DP_MST:
5360 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5361 return port_to_aux_power_domain(intel_dig_port->port);
5362 default:
5363 MISSING_CASE(intel_encoder->type);
5364 return POWER_DOMAIN_AUX_A;
5365 }
5366}
5367
5368static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5369{
5370 struct drm_device *dev = crtc->dev;
5371 struct intel_encoder *intel_encoder;
5372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5373 enum i915_pipe pipe = intel_crtc->pipe;
5374 unsigned long mask;
5375 enum transcoder transcoder;
5376
5377 if (!crtc->state->active)
5378 return 0;
5379
5380 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5381
5382 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5383 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5384 if (intel_crtc->config->pch_pfit.enabled ||
5385 intel_crtc->config->pch_pfit.force_thru)
5386 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5387
5388 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5389 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5390
5391 return mask;
5392}
5393
5394static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5395{
5396 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5398 enum intel_display_power_domain domain;
5399 unsigned long domains, new_domains, old_domains;
5400
5401 old_domains = intel_crtc->enabled_power_domains;
5402 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5403
5404 domains = new_domains & ~old_domains;
5405
5406 for_each_power_domain(domain, domains)
5407 intel_display_power_get(dev_priv, domain);
5408
5409 return old_domains & ~new_domains;
5410}
5411
5412static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5413 unsigned long domains)
5414{
5415 enum intel_display_power_domain domain;
5416
5417 for_each_power_domain(domain, domains)
5418 intel_display_power_put(dev_priv, domain);
5419}
5420
5421static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5422{
5423 struct drm_device *dev = state->dev;
5424 struct drm_i915_private *dev_priv = dev->dev_private;
5425 unsigned long put_domains[I915_MAX_PIPES] = {};
5426 struct drm_crtc_state *crtc_state;
5427 struct drm_crtc *crtc;
5428 int i;
5429
5430 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5431 if (needs_modeset(crtc->state))
5432 put_domains[to_intel_crtc(crtc)->pipe] =
5433 modeset_get_crtc_power_domains(crtc);
5434 }
5435
5436 if (dev_priv->display.modeset_commit_cdclk) {
5437 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5438
5439 if (cdclk != dev_priv->cdclk_freq &&
5440 !WARN_ON(!state->allow_modeset))
5441 dev_priv->display.modeset_commit_cdclk(state);
5442 }
5443
5444 for (i = 0; i < I915_MAX_PIPES; i++)
5445 if (put_domains[i])
5446 modeset_put_power_domains(dev_priv, put_domains[i]);
5447}
5448
5449static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5450{
5451 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5452
5453 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5454 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5455 return max_cdclk_freq;
5456 else if (IS_CHERRYVIEW(dev_priv))
5457 return max_cdclk_freq*95/100;
5458 else if (INTEL_INFO(dev_priv)->gen < 4)
5459 return 2*max_cdclk_freq*90/100;
5460 else
5461 return max_cdclk_freq*90/100;
5462}
5463
5464static void intel_update_max_cdclk(struct drm_device *dev)
5465{
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467
5468 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5469 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5470
5471 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5472 dev_priv->max_cdclk_freq = 675000;
5473 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5474 dev_priv->max_cdclk_freq = 540000;
5475 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5476 dev_priv->max_cdclk_freq = 450000;
5477 else
5478 dev_priv->max_cdclk_freq = 337500;
5479 } else if (IS_BROADWELL(dev)) {
5480 /*
5481 * FIXME with extra cooling we can allow
5482 * 540 MHz for ULX and 675 Mhz for ULT.
5483 * How can we know if extra cooling is
5484 * available? PCI ID, VTB, something else?
5485 */
5486 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5487 dev_priv->max_cdclk_freq = 450000;
5488 else if (IS_BDW_ULX(dev))
5489 dev_priv->max_cdclk_freq = 450000;
5490 else if (IS_BDW_ULT(dev))
5491 dev_priv->max_cdclk_freq = 540000;
5492 else
5493 dev_priv->max_cdclk_freq = 675000;
5494 } else if (IS_CHERRYVIEW(dev)) {
5495 dev_priv->max_cdclk_freq = 320000;
5496 } else if (IS_VALLEYVIEW(dev)) {
5497 dev_priv->max_cdclk_freq = 400000;
5498 } else {
5499 /* otherwise assume cdclk is fixed */
5500 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5501 }
5502
5503 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5504
5505 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5506 dev_priv->max_cdclk_freq);
5507
5508 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5509 dev_priv->max_dotclk_freq);
5510}
5511
5512static void intel_update_cdclk(struct drm_device *dev)
5513{
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515
5516 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5517 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5518 dev_priv->cdclk_freq);
5519
5520 /*
5521 * Program the gmbus_freq based on the cdclk frequency.
5522 * BSpec erroneously claims we should aim for 4MHz, but
5523 * in fact 1MHz is the correct frequency.
5524 */
5525 if (IS_VALLEYVIEW(dev)) {
5526 /*
5527 * Program the gmbus_freq based on the cdclk frequency.
5528 * BSpec erroneously claims we should aim for 4MHz, but
5529 * in fact 1MHz is the correct frequency.
5530 */
5531 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5532 }
5533
5534 if (dev_priv->max_cdclk_freq == 0)
5535 intel_update_max_cdclk(dev);
5536}
5537
5538static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5539{
5540 struct drm_i915_private *dev_priv = dev->dev_private;
5541 uint32_t divider;
5542 uint32_t ratio;
5543 uint32_t current_freq;
5544 int ret;
5545
5546 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5547 switch (frequency) {
5548 case 144000:
5549 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5550 ratio = BXT_DE_PLL_RATIO(60);
5551 break;
5552 case 288000:
5553 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5554 ratio = BXT_DE_PLL_RATIO(60);
5555 break;
5556 case 384000:
5557 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5558 ratio = BXT_DE_PLL_RATIO(60);
5559 break;
5560 case 576000:
5561 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5562 ratio = BXT_DE_PLL_RATIO(60);
5563 break;
5564 case 624000:
5565 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5566 ratio = BXT_DE_PLL_RATIO(65);
5567 break;
5568 case 19200:
5569 /*
5570 * Bypass frequency with DE PLL disabled. Init ratio, divider
5571 * to suppress GCC warning.
5572 */
5573 ratio = 0;
5574 divider = 0;
5575 break;
5576 default:
5577 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5578
5579 return;
5580 }
5581
5582 mutex_lock(&dev_priv->rps.hw_lock);
5583 /* Inform power controller of upcoming frequency change */
5584 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5585 0x80000000);
5586 mutex_unlock(&dev_priv->rps.hw_lock);
5587
5588 if (ret) {
5589 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5590 ret, frequency);
5591 return;
5592 }
5593
5594 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5595 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5596 current_freq = current_freq * 500 + 1000;
5597
5598 /*
5599 * DE PLL has to be disabled when
5600 * - setting to 19.2MHz (bypass, PLL isn't used)
5601 * - before setting to 624MHz (PLL needs toggling)
5602 * - before setting to any frequency from 624MHz (PLL needs toggling)
5603 */
5604 if (frequency == 19200 || frequency == 624000 ||
5605 current_freq == 624000) {
5606 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5607 /* Timeout 200us */
5608 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5609 1))
5610 DRM_ERROR("timout waiting for DE PLL unlock\n");
5611 }
5612
5613 if (frequency != 19200) {
5614 uint32_t val;
5615
5616 val = I915_READ(BXT_DE_PLL_CTL);
5617 val &= ~BXT_DE_PLL_RATIO_MASK;
5618 val |= ratio;
5619 I915_WRITE(BXT_DE_PLL_CTL, val);
5620
5621 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5622 /* Timeout 200us */
5623 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5624 DRM_ERROR("timeout waiting for DE PLL lock\n");
5625
5626 val = I915_READ(CDCLK_CTL);
5627 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5628 val |= divider;
5629 /*
5630 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5631 * enable otherwise.
5632 */
5633 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5634 if (frequency >= 500000)
5635 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5636
5637 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5638 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5639 val |= (frequency - 1000) / 500;
5640 I915_WRITE(CDCLK_CTL, val);
5641 }
5642
5643 mutex_lock(&dev_priv->rps.hw_lock);
5644 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5645 DIV_ROUND_UP(frequency, 25000));
5646 mutex_unlock(&dev_priv->rps.hw_lock);
5647
5648 if (ret) {
5649 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5650 ret, frequency);
5651 return;
5652 }
5653
5654 intel_update_cdclk(dev);
5655}
5656
5657void broxton_init_cdclk(struct drm_device *dev)
5658{
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 uint32_t val;
5661
5662 /*
5663 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5664 * or else the reset will hang because there is no PCH to respond.
5665 * Move the handshake programming to initialization sequence.
5666 * Previously was left up to BIOS.
5667 */
5668 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5669 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5670 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5671
5672 /* Enable PG1 for cdclk */
5673 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5674
5675 /* check if cd clock is enabled */
5676 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5677 DRM_DEBUG_KMS("Display already initialized\n");
5678 return;
5679 }
5680
5681 /*
5682 * FIXME:
5683 * - The initial CDCLK needs to be read from VBT.
5684 * Need to make this change after VBT has changes for BXT.
5685 * - check if setting the max (or any) cdclk freq is really necessary
5686 * here, it belongs to modeset time
5687 */
5688 broxton_set_cdclk(dev, 624000);
5689
5690 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5691 POSTING_READ(DBUF_CTL);
5692
5693 udelay(10);
5694
5695 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5696 DRM_ERROR("DBuf power enable timeout!\n");
5697}
5698
5699void broxton_uninit_cdclk(struct drm_device *dev)
5700{
5701 struct drm_i915_private *dev_priv = dev->dev_private;
5702
5703 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5704 POSTING_READ(DBUF_CTL);
5705
5706 udelay(10);
5707
5708 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5709 DRM_ERROR("DBuf power disable timeout!\n");
5710
5711 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5712 broxton_set_cdclk(dev, 19200);
5713
5714 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5715}
5716
5717static const struct skl_cdclk_entry {
5718 unsigned int freq;
5719 unsigned int vco;
5720} skl_cdclk_frequencies[] = {
5721 { .freq = 308570, .vco = 8640 },
5722 { .freq = 337500, .vco = 8100 },
5723 { .freq = 432000, .vco = 8640 },
5724 { .freq = 450000, .vco = 8100 },
5725 { .freq = 540000, .vco = 8100 },
5726 { .freq = 617140, .vco = 8640 },
5727 { .freq = 675000, .vco = 8100 },
5728};
5729
5730static unsigned int skl_cdclk_decimal(unsigned int freq)
5731{
5732 return (freq - 1000) / 500;
5733}
5734
5735static unsigned int skl_cdclk_get_vco(unsigned int freq)
5736{
5737 unsigned int i;
5738
5739 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5740 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5741
5742 if (e->freq == freq)
5743 return e->vco;
5744 }
5745
5746 return 8100;
5747}
5748
5749static void
5750skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5751{
5752 unsigned int min_freq;
5753 u32 val;
5754
5755 /* select the minimum CDCLK before enabling DPLL 0 */
5756 val = I915_READ(CDCLK_CTL);
5757 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5758 val |= CDCLK_FREQ_337_308;
5759
5760 if (required_vco == 8640)
5761 min_freq = 308570;
5762 else
5763 min_freq = 337500;
5764
5765 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5766
5767 I915_WRITE(CDCLK_CTL, val);
5768 POSTING_READ(CDCLK_CTL);
5769
5770 /*
5771 * We always enable DPLL0 with the lowest link rate possible, but still
5772 * taking into account the VCO required to operate the eDP panel at the
5773 * desired frequency. The usual DP link rates operate with a VCO of
5774 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5775 * The modeset code is responsible for the selection of the exact link
5776 * rate later on, with the constraint of choosing a frequency that
5777 * works with required_vco.
5778 */
5779 val = I915_READ(DPLL_CTRL1);
5780
5781 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5782 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5783 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5784 if (required_vco == 8640)
5785 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5786 SKL_DPLL0);
5787 else
5788 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5789 SKL_DPLL0);
5790
5791 I915_WRITE(DPLL_CTRL1, val);
5792 POSTING_READ(DPLL_CTRL1);
5793
5794 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5795
5796 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5797 DRM_ERROR("DPLL0 not locked\n");
5798}
5799
5800static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5801{
5802 int ret;
5803 u32 val;
5804
5805 /* inform PCU we want to change CDCLK */
5806 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5807 mutex_lock(&dev_priv->rps.hw_lock);
5808 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5809 mutex_unlock(&dev_priv->rps.hw_lock);
5810
5811 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5812}
5813
5814static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5815{
5816 unsigned int i;
5817
5818 for (i = 0; i < 15; i++) {
5819 if (skl_cdclk_pcu_ready(dev_priv))
5820 return true;
5821 udelay(10);
5822 }
5823
5824 return false;
5825}
5826
5827static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5828{
5829 struct drm_device *dev = dev_priv->dev;
5830 u32 freq_select, pcu_ack;
5831
5832 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5833
5834 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5835 DRM_ERROR("failed to inform PCU about cdclk change\n");
5836 return;
5837 }
5838
5839 /* set CDCLK_CTL */
5840 switch(freq) {
5841 case 450000:
5842 case 432000:
5843 freq_select = CDCLK_FREQ_450_432;
5844 pcu_ack = 1;
5845 break;
5846 case 540000:
5847 freq_select = CDCLK_FREQ_540;
5848 pcu_ack = 2;
5849 break;
5850 case 308570:
5851 case 337500:
5852 default:
5853 freq_select = CDCLK_FREQ_337_308;
5854 pcu_ack = 0;
5855 break;
5856 case 617140:
5857 case 675000:
5858 freq_select = CDCLK_FREQ_675_617;
5859 pcu_ack = 3;
5860 break;
5861 }
5862
5863 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5864 POSTING_READ(CDCLK_CTL);
5865
5866 /* inform PCU of the change */
5867 mutex_lock(&dev_priv->rps.hw_lock);
5868 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5869 mutex_unlock(&dev_priv->rps.hw_lock);
5870
5871 intel_update_cdclk(dev);
5872}
5873
5874void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5875{
5876 /* disable DBUF power */
5877 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5878 POSTING_READ(DBUF_CTL);
5879
5880 udelay(10);
5881
5882 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5883 DRM_ERROR("DBuf power disable timeout\n");
5884
5885 /*
5886 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5887 */
5888 if (dev_priv->csr.dmc_payload) {
5889 /* disable DPLL0 */
5890 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5891 ~LCPLL_PLL_ENABLE);
5892 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5893 DRM_ERROR("Couldn't disable DPLL0\n");
5894 }
5895
5896 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5897}
5898
5899void skl_init_cdclk(struct drm_i915_private *dev_priv)
5900{
5901 u32 val;
5902 unsigned int required_vco;
5903
5904 /* enable PCH reset handshake */
5905 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5906 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5907
5908 /* enable PG1 and Misc I/O */
5909 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5910
5911 /* DPLL0 not enabled (happens on early BIOS versions) */
5912 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5913 /* enable DPLL0 */
5914 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5915 skl_dpll0_enable(dev_priv, required_vco);
5916 }
5917
5918 /* set CDCLK to the frequency the BIOS chose */
5919 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5920
5921 /* enable DBUF power */
5922 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5923 POSTING_READ(DBUF_CTL);
5924
5925 udelay(10);
5926
5927 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5928 DRM_ERROR("DBuf power enable timeout\n");
5929}
5930
5931/* Adjust CDclk dividers to allow high res or save power if possible */
5932static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5933{
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 u32 val, cmd;
5936
5937 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5938 != dev_priv->cdclk_freq);
5939
5940 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5941 cmd = 2;
5942 else if (cdclk == 266667)
5943 cmd = 1;
5944 else
5945 cmd = 0;
5946
5947 mutex_lock(&dev_priv->rps.hw_lock);
5948 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5949 val &= ~DSPFREQGUAR_MASK;
5950 val |= (cmd << DSPFREQGUAR_SHIFT);
5951 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5952 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5953 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5954 50)) {
5955 DRM_ERROR("timed out waiting for CDclk change\n");
5956 }
5957 mutex_unlock(&dev_priv->rps.hw_lock);
5958
5959 mutex_lock(&dev_priv->sb_lock);
5960
5961 if (cdclk == 400000) {
5962 u32 divider;
5963
5964 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5965
5966 /* adjust cdclk divider */
5967 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5968 val &= ~CCK_FREQUENCY_VALUES;
5969 val |= divider;
5970 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5971
5972 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5973 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5974 50))
5975 DRM_ERROR("timed out waiting for CDclk change\n");
5976 }
5977
5978 /* adjust self-refresh exit latency value */
5979 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5980 val &= ~0x7f;
5981
5982 /*
5983 * For high bandwidth configs, we set a higher latency in the bunit
5984 * so that the core display fetch happens in time to avoid underruns.
5985 */
5986 if (cdclk == 400000)
5987 val |= 4500 / 250; /* 4.5 usec */
5988 else
5989 val |= 3000 / 250; /* 3.0 usec */
5990 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5991
5992 mutex_unlock(&dev_priv->sb_lock);
5993
5994 intel_update_cdclk(dev);
5995}
5996
5997static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5998{
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000 u32 val, cmd;
6001
6002 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6003 != dev_priv->cdclk_freq);
6004
6005 switch (cdclk) {
6006 case 333333:
6007 case 320000:
6008 case 266667:
6009 case 200000:
6010 break;
6011 default:
6012 MISSING_CASE(cdclk);
6013 return;
6014 }
6015
6016 /*
6017 * Specs are full of misinformation, but testing on actual
6018 * hardware has shown that we just need to write the desired
6019 * CCK divider into the Punit register.
6020 */
6021 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6022
6023 mutex_lock(&dev_priv->rps.hw_lock);
6024 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6025 val &= ~DSPFREQGUAR_MASK_CHV;
6026 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6027 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6028 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6029 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6030 50)) {
6031 DRM_ERROR("timed out waiting for CDclk change\n");
6032 }
6033 mutex_unlock(&dev_priv->rps.hw_lock);
6034
6035 intel_update_cdclk(dev);
6036}
6037
6038static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6039 int max_pixclk)
6040{
6041 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6042 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6043
6044 /*
6045 * Really only a few cases to deal with, as only 4 CDclks are supported:
6046 * 200MHz
6047 * 267MHz
6048 * 320/333MHz (depends on HPLL freq)
6049 * 400MHz (VLV only)
6050 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6051 * of the lower bin and adjust if needed.
6052 *
6053 * We seem to get an unstable or solid color picture at 200MHz.
6054 * Not sure what's wrong. For now use 200MHz only when all pipes
6055 * are off.
6056 */
6057 if (!IS_CHERRYVIEW(dev_priv) &&
6058 max_pixclk > freq_320*limit/100)
6059 return 400000;
6060 else if (max_pixclk > 266667*limit/100)
6061 return freq_320;
6062 else if (max_pixclk > 0)
6063 return 266667;
6064 else
6065 return 200000;
6066}
6067
6068static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6069 int max_pixclk)
6070{
6071 /*
6072 * FIXME:
6073 * - remove the guardband, it's not needed on BXT
6074 * - set 19.2MHz bypass frequency if there are no active pipes
6075 */
6076 if (max_pixclk > 576000*9/10)
6077 return 624000;
6078 else if (max_pixclk > 384000*9/10)
6079 return 576000;
6080 else if (max_pixclk > 288000*9/10)
6081 return 384000;
6082 else if (max_pixclk > 144000*9/10)
6083 return 288000;
6084 else
6085 return 144000;
6086}
6087
6088/* Compute the max pixel clock for new configuration. Uses atomic state if
6089 * that's non-NULL, look at current state otherwise. */
6090static int intel_mode_max_pixclk(struct drm_device *dev,
6091 struct drm_atomic_state *state)
6092{
6093 struct intel_crtc *intel_crtc;
6094 struct intel_crtc_state *crtc_state;
6095 int max_pixclk = 0;
6096
6097 for_each_intel_crtc(dev, intel_crtc) {
6098 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6099 if (IS_ERR(crtc_state))
6100 return PTR_ERR(crtc_state);
6101
6102 if (!crtc_state->base.enable)
6103 continue;
6104
6105 max_pixclk = max(max_pixclk,
6106 crtc_state->base.adjusted_mode.crtc_clock);
6107 }
6108
6109 return max_pixclk;
6110}
6111
6112static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6113{
6114 struct drm_device *dev = state->dev;
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116 int max_pixclk = intel_mode_max_pixclk(dev, state);
6117
6118 if (max_pixclk < 0)
6119 return max_pixclk;
6120
6121 to_intel_atomic_state(state)->cdclk =
6122 valleyview_calc_cdclk(dev_priv, max_pixclk);
6123
6124 return 0;
6125}
6126
6127static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6128{
6129 struct drm_device *dev = state->dev;
6130 struct drm_i915_private *dev_priv = dev->dev_private;
6131 int max_pixclk = intel_mode_max_pixclk(dev, state);
6132
6133 if (max_pixclk < 0)
6134 return max_pixclk;
6135
6136 to_intel_atomic_state(state)->cdclk =
6137 broxton_calc_cdclk(dev_priv, max_pixclk);
6138
6139 return 0;
6140}
6141
6142static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6143{
6144 unsigned int credits, default_credits;
6145
6146 if (IS_CHERRYVIEW(dev_priv))
6147 default_credits = PFI_CREDIT(12);
6148 else
6149 default_credits = PFI_CREDIT(8);
6150
6151 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6152 /* CHV suggested value is 31 or 63 */
6153 if (IS_CHERRYVIEW(dev_priv))
6154 credits = PFI_CREDIT_63;
6155 else
6156 credits = PFI_CREDIT(15);
6157 } else {
6158 credits = default_credits;
6159 }
6160
6161 /*
6162 * WA - write default credits before re-programming
6163 * FIXME: should we also set the resend bit here?
6164 */
6165 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6166 default_credits);
6167
6168 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6169 credits | PFI_CREDIT_RESEND);
6170
6171 /*
6172 * FIXME is this guaranteed to clear
6173 * immediately or should we poll for it?
6174 */
6175 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6176}
6177
6178static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6179{
6180 struct drm_device *dev = old_state->dev;
6181 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183
6184 /*
6185 * FIXME: We can end up here with all power domains off, yet
6186 * with a CDCLK frequency other than the minimum. To account
6187 * for this take the PIPE-A power domain, which covers the HW
6188 * blocks needed for the following programming. This can be
6189 * removed once it's guaranteed that we get here either with
6190 * the minimum CDCLK set, or the required power domains
6191 * enabled.
6192 */
6193 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6194
6195 if (IS_CHERRYVIEW(dev))
6196 cherryview_set_cdclk(dev, req_cdclk);
6197 else
6198 valleyview_set_cdclk(dev, req_cdclk);
6199
6200 vlv_program_pfi_credits(dev_priv);
6201
6202 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6203}
6204
6205static void valleyview_crtc_enable(struct drm_crtc *crtc)
6206{
6207 struct drm_device *dev = crtc->dev;
6208 struct drm_i915_private *dev_priv = to_i915(dev);
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 struct intel_encoder *encoder;
6211 int pipe = intel_crtc->pipe;
6212 bool is_dsi;
6213
6214 if (WARN_ON(intel_crtc->active))
6215 return;
6216
6217 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6218
6219 if (intel_crtc->config->has_dp_encoder)
6220 intel_dp_set_m_n(intel_crtc, M1_N1);
6221
6222 intel_set_pipe_timings(intel_crtc);
6223
6224 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6225 struct drm_i915_private *dev_priv = dev->dev_private;
6226
6227 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6228 I915_WRITE(CHV_CANVAS(pipe), 0);
6229 }
6230
6231 i9xx_set_pipeconf(intel_crtc);
6232
6233 intel_crtc->active = true;
6234
6235 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6236
6237 for_each_encoder_on_crtc(dev, crtc, encoder)
6238 if (encoder->pre_pll_enable)
6239 encoder->pre_pll_enable(encoder);
6240
6241 if (!is_dsi) {
6242 if (IS_CHERRYVIEW(dev)) {
6243 chv_prepare_pll(intel_crtc, intel_crtc->config);
6244 chv_enable_pll(intel_crtc, intel_crtc->config);
6245 } else {
6246 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6247 vlv_enable_pll(intel_crtc, intel_crtc->config);
6248 }
6249 }
6250
6251 for_each_encoder_on_crtc(dev, crtc, encoder)
6252 if (encoder->pre_enable)
6253 encoder->pre_enable(encoder);
6254
6255 i9xx_pfit_enable(intel_crtc);
6256
6257 intel_crtc_load_lut(crtc);
6258
6259 intel_enable_pipe(intel_crtc);
6260
6261 assert_vblank_disabled(crtc);
6262 drm_crtc_vblank_on(crtc);
6263
6264 for_each_encoder_on_crtc(dev, crtc, encoder)
6265 encoder->enable(encoder);
6266}
6267
6268static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6269{
6270 struct drm_device *dev = crtc->base.dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272
6273 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6274 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6275}
6276
6277static void i9xx_crtc_enable(struct drm_crtc *crtc)
6278{
6279 struct drm_device *dev = crtc->dev;
6280 struct drm_i915_private *dev_priv = to_i915(dev);
6281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6282 struct intel_encoder *encoder;
6283 int pipe = intel_crtc->pipe;
6284
6285 if (WARN_ON(intel_crtc->active))
6286 return;
6287
6288 i9xx_set_pll_dividers(intel_crtc);
6289
6290 if (intel_crtc->config->has_dp_encoder)
6291 intel_dp_set_m_n(intel_crtc, M1_N1);
6292
6293 intel_set_pipe_timings(intel_crtc);
6294
6295 i9xx_set_pipeconf(intel_crtc);
6296
6297 intel_crtc->active = true;
6298
6299 if (!IS_GEN2(dev))
6300 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6301
6302 for_each_encoder_on_crtc(dev, crtc, encoder)
6303 if (encoder->pre_enable)
6304 encoder->pre_enable(encoder);
6305
6306 i9xx_enable_pll(intel_crtc);
6307
6308 i9xx_pfit_enable(intel_crtc);
6309
6310 intel_crtc_load_lut(crtc);
6311
6312 intel_update_watermarks(crtc);
6313 intel_enable_pipe(intel_crtc);
6314
6315 assert_vblank_disabled(crtc);
6316 drm_crtc_vblank_on(crtc);
6317
6318 for_each_encoder_on_crtc(dev, crtc, encoder)
6319 encoder->enable(encoder);
6320}
6321
6322static void i9xx_pfit_disable(struct intel_crtc *crtc)
6323{
6324 struct drm_device *dev = crtc->base.dev;
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326
6327 if (!crtc->config->gmch_pfit.control)
6328 return;
6329
6330 assert_pipe_disabled(dev_priv, crtc->pipe);
6331
6332 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6333 I915_READ(PFIT_CONTROL));
6334 I915_WRITE(PFIT_CONTROL, 0);
6335}
6336
6337static void i9xx_crtc_disable(struct drm_crtc *crtc)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342 struct intel_encoder *encoder;
6343 int pipe = intel_crtc->pipe;
6344
6345 /*
6346 * On gen2 planes are double buffered but the pipe isn't, so we must
6347 * wait for planes to fully turn off before disabling the pipe.
6348 * We also need to wait on all gmch platforms because of the
6349 * self-refresh mode constraint explained above.
6350 */
6351 intel_wait_for_vblank(dev, pipe);
6352
6353 for_each_encoder_on_crtc(dev, crtc, encoder)
6354 encoder->disable(encoder);
6355
6356 drm_crtc_vblank_off(crtc);
6357 assert_vblank_disabled(crtc);
6358
6359 intel_disable_pipe(intel_crtc);
6360
6361 i9xx_pfit_disable(intel_crtc);
6362
6363 for_each_encoder_on_crtc(dev, crtc, encoder)
6364 if (encoder->post_disable)
6365 encoder->post_disable(encoder);
6366
6367 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6368 if (IS_CHERRYVIEW(dev))
6369 chv_disable_pll(dev_priv, pipe);
6370 else if (IS_VALLEYVIEW(dev))
6371 vlv_disable_pll(dev_priv, pipe);
6372 else
6373 i9xx_disable_pll(intel_crtc);
6374 }
6375
6376 for_each_encoder_on_crtc(dev, crtc, encoder)
6377 if (encoder->post_pll_disable)
6378 encoder->post_pll_disable(encoder);
6379
6380 if (!IS_GEN2(dev))
6381 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6382}
6383
6384static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6385{
6386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6388 enum intel_display_power_domain domain;
6389 unsigned long domains;
6390
6391 if (!intel_crtc->active)
6392 return;
6393
6394 if (to_intel_plane_state(crtc->primary->state)->visible) {
6395 intel_crtc_wait_for_pending_flips(crtc);
6396 intel_pre_disable_primary(crtc);
6397
6398 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6399 to_intel_plane_state(crtc->primary->state)->visible = false;
6400 }
6401
6402 dev_priv->display.crtc_disable(crtc);
6403 intel_crtc->active = false;
6404 intel_update_watermarks(crtc);
6405 intel_disable_shared_dpll(intel_crtc);
6406
6407 domains = intel_crtc->enabled_power_domains;
6408 for_each_power_domain(domain, domains)
6409 intel_display_power_put(dev_priv, domain);
6410 intel_crtc->enabled_power_domains = 0;
6411}
6412
6413/*
6414 * turn all crtc's off, but do not adjust state
6415 * This has to be paired with a call to intel_modeset_setup_hw_state.
6416 */
6417int intel_display_suspend(struct drm_device *dev)
6418{
6419 struct drm_mode_config *config = &dev->mode_config;
6420 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6421 struct drm_atomic_state *state;
6422 struct drm_crtc *crtc;
6423 unsigned crtc_mask = 0;
6424 int ret = 0;
6425
6426 if (WARN_ON(!ctx))
6427 return 0;
6428
6429 lockdep_assert_held(&ctx->ww_ctx);
6430 state = drm_atomic_state_alloc(dev);
6431 if (WARN_ON(!state))
6432 return -ENOMEM;
6433
6434 state->acquire_ctx = ctx;
6435 state->allow_modeset = true;
6436
6437 for_each_crtc(dev, crtc) {
6438 struct drm_crtc_state *crtc_state =
6439 drm_atomic_get_crtc_state(state, crtc);
6440
6441 ret = PTR_ERR_OR_ZERO(crtc_state);
6442 if (ret)
6443 goto free;
6444
6445 if (!crtc_state->active)
6446 continue;
6447
6448 crtc_state->active = false;
6449 crtc_mask |= 1 << drm_crtc_index(crtc);
6450 }
6451
6452 if (crtc_mask) {
6453 ret = drm_atomic_commit(state);
6454
6455 if (!ret) {
6456 for_each_crtc(dev, crtc)
6457 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6458 crtc->state->active = true;
6459
6460 return ret;
6461 }
6462 }
6463
6464free:
6465 if (ret)
6466 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6467 drm_atomic_state_free(state);
6468 return ret;
6469}
6470
6471void intel_encoder_destroy(struct drm_encoder *encoder)
6472{
6473 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6474
6475 drm_encoder_cleanup(encoder);
6476 kfree(intel_encoder);
6477}
6478
6479/* Cross check the actual hw state with our own modeset state tracking (and it's
6480 * internal consistency). */
6481static void intel_connector_check_state(struct intel_connector *connector)
6482{
6483 struct drm_crtc *crtc = connector->base.state->crtc;
6484
6485 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6486 connector->base.base.id,
6487 connector->base.name);
6488
6489 if (connector->get_hw_state(connector)) {
6490 struct intel_encoder *encoder = connector->encoder;
6491 struct drm_connector_state *conn_state = connector->base.state;
6492
6493 I915_STATE_WARN(!crtc,
6494 "connector enabled without attached crtc\n");
6495
6496 if (!crtc)
6497 return;
6498
6499 I915_STATE_WARN(!crtc->state->active,
6500 "connector is active, but attached crtc isn't\n");
6501
6502 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6503 return;
6504
6505 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6506 "atomic encoder doesn't match attached encoder\n");
6507
6508 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6509 "attached encoder crtc differs from connector crtc\n");
6510 } else {
6511 I915_STATE_WARN(crtc && crtc->state->active,
6512 "attached crtc is active, but connector isn't\n");
6513 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6514 "best encoder set without crtc!\n");
6515 }
6516}
6517
6518int intel_connector_init(struct intel_connector *connector)
6519{
6520 struct drm_connector_state *connector_state;
6521
6522 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6523 if (!connector_state)
6524 return -ENOMEM;
6525
6526 connector->base.state = connector_state;
6527 return 0;
6528}
6529
6530struct intel_connector *intel_connector_alloc(void)
6531{
6532 struct intel_connector *connector;
6533
6534 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6535 if (!connector)
6536 return NULL;
6537
6538 if (intel_connector_init(connector) < 0) {
6539 kfree(connector);
6540 return NULL;
6541 }
6542
6543 return connector;
6544}
6545
6546/* Simple connector->get_hw_state implementation for encoders that support only
6547 * one connector and no cloning and hence the encoder state determines the state
6548 * of the connector. */
6549bool intel_connector_get_hw_state(struct intel_connector *connector)
6550{
6551 enum i915_pipe pipe = 0;
6552 struct intel_encoder *encoder = connector->encoder;
6553
6554 return encoder->get_hw_state(encoder, &pipe);
6555}
6556
6557static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6558{
6559 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6560 return crtc_state->fdi_lanes;
6561
6562 return 0;
6563}
6564
6565static int ironlake_check_fdi_lanes(struct drm_device *dev, enum i915_pipe pipe,
6566 struct intel_crtc_state *pipe_config)
6567{
6568 struct drm_atomic_state *state = pipe_config->base.state;
6569 struct intel_crtc *other_crtc;
6570 struct intel_crtc_state *other_crtc_state;
6571
6572 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6573 pipe_name(pipe), pipe_config->fdi_lanes);
6574 if (pipe_config->fdi_lanes > 4) {
6575 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6576 pipe_name(pipe), pipe_config->fdi_lanes);
6577 return -EINVAL;
6578 }
6579
6580 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6581 if (pipe_config->fdi_lanes > 2) {
6582 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6583 pipe_config->fdi_lanes);
6584 return -EINVAL;
6585 } else {
6586 return 0;
6587 }
6588 }
6589
6590 if (INTEL_INFO(dev)->num_pipes == 2)
6591 return 0;
6592
6593 /* Ivybridge 3 pipe is really complicated */
6594 switch (pipe) {
6595 case PIPE_A:
6596 return 0;
6597 case PIPE_B:
6598 if (pipe_config->fdi_lanes <= 2)
6599 return 0;
6600
6601 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6602 other_crtc_state =
6603 intel_atomic_get_crtc_state(state, other_crtc);
6604 if (IS_ERR(other_crtc_state))
6605 return PTR_ERR(other_crtc_state);
6606
6607 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6608 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6609 pipe_name(pipe), pipe_config->fdi_lanes);
6610 return -EINVAL;
6611 }
6612 return 0;
6613 case PIPE_C:
6614 if (pipe_config->fdi_lanes > 2) {
6615 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6616 pipe_name(pipe), pipe_config->fdi_lanes);
6617 return -EINVAL;
6618 }
6619
6620 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6621 other_crtc_state =
6622 intel_atomic_get_crtc_state(state, other_crtc);
6623 if (IS_ERR(other_crtc_state))
6624 return PTR_ERR(other_crtc_state);
6625
6626 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6627 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6628 return -EINVAL;
6629 }
6630 return 0;
6631 default:
6632 BUG();
6633 }
6634}
6635
6636#define RETRY 1
6637static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6638 struct intel_crtc_state *pipe_config)
6639{
6640 struct drm_device *dev = intel_crtc->base.dev;
6641 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6642 int lane, link_bw, fdi_dotclock, ret;
6643 bool needs_recompute = false;
6644
6645retry:
6646 /* FDI is a binary signal running at ~2.7GHz, encoding
6647 * each output octet as 10 bits. The actual frequency
6648 * is stored as a divider into a 100MHz clock, and the
6649 * mode pixel clock is stored in units of 1KHz.
6650 * Hence the bw of each lane in terms of the mode signal
6651 * is:
6652 */
6653 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6654
6655 fdi_dotclock = adjusted_mode->crtc_clock;
6656
6657 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6658 pipe_config->pipe_bpp);
6659
6660 pipe_config->fdi_lanes = lane;
6661
6662 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6663 link_bw, &pipe_config->fdi_m_n);
6664
6665 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6666 intel_crtc->pipe, pipe_config);
6667 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6668 pipe_config->pipe_bpp -= 2*3;
6669 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6670 pipe_config->pipe_bpp);
6671 needs_recompute = true;
6672 pipe_config->bw_constrained = true;
6673
6674 goto retry;
6675 }
6676
6677 if (needs_recompute)
6678 return RETRY;
6679
6680 return ret;
6681}
6682
6683static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6684 struct intel_crtc_state *pipe_config)
6685{
6686 if (pipe_config->pipe_bpp > 24)
6687 return false;
6688
6689 /* HSW can handle pixel rate up to cdclk? */
6690 if (IS_HASWELL(dev_priv->dev))
6691 return true;
6692
6693 /*
6694 * We compare against max which means we must take
6695 * the increased cdclk requirement into account when
6696 * calculating the new cdclk.
6697 *
6698 * Should measure whether using a lower cdclk w/o IPS
6699 */
6700 return ilk_pipe_pixel_rate(pipe_config) <=
6701 dev_priv->max_cdclk_freq * 95 / 100;
6702}
6703
6704static void hsw_compute_ips_config(struct intel_crtc *crtc,
6705 struct intel_crtc_state *pipe_config)
6706{
6707 struct drm_device *dev = crtc->base.dev;
6708 struct drm_i915_private *dev_priv = dev->dev_private;
6709
6710 pipe_config->ips_enabled = i915.enable_ips &&
6711 hsw_crtc_supports_ips(crtc) &&
6712 pipe_config_supports_ips(dev_priv, pipe_config);
6713}
6714
6715static int intel_crtc_compute_config(struct intel_crtc *crtc,
6716 struct intel_crtc_state *pipe_config)
6717{
6718 struct drm_device *dev = crtc->base.dev;
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6721
6722 /* FIXME should check pixel clock limits on all platforms */
6723 if (INTEL_INFO(dev)->gen < 4) {
6724 int clock_limit = dev_priv->max_cdclk_freq;
6725
6726 /*
6727 * Enable pixel doubling when the dot clock
6728 * is > 90% of the (display) core speed.
6729 *
6730 * GDG double wide on either pipe,
6731 * otherwise pipe A only.
6732 */
6733 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6734 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6735 clock_limit *= 2;
6736 pipe_config->double_wide = true;
6737 }
6738
6739 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6740 return -EINVAL;
6741 }
6742
6743 /*
6744 * Pipe horizontal size must be even in:
6745 * - DVO ganged mode
6746 * - LVDS dual channel mode
6747 * - Double wide pipe
6748 */
6749 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6750 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6751 pipe_config->pipe_src_w &= ~1;
6752
6753 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6754 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6755 */
6756 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6757 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6758 return -EINVAL;
6759
6760 if (HAS_IPS(dev))
6761 hsw_compute_ips_config(crtc, pipe_config);
6762
6763 if (pipe_config->has_pch_encoder)
6764 return ironlake_fdi_compute_config(crtc, pipe_config);
6765
6766 return 0;
6767}
6768
6769static int skylake_get_display_clock_speed(struct drm_device *dev)
6770{
6771 struct drm_i915_private *dev_priv = to_i915(dev);
6772 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6773 uint32_t cdctl = I915_READ(CDCLK_CTL);
6774 uint32_t linkrate;
6775
6776 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6777 return 24000; /* 24MHz is the cd freq with NSSC ref */
6778
6779 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6780 return 540000;
6781
6782 linkrate = (I915_READ(DPLL_CTRL1) &
6783 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6784
6785 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6786 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6787 /* vco 8640 */
6788 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6789 case CDCLK_FREQ_450_432:
6790 return 432000;
6791 case CDCLK_FREQ_337_308:
6792 return 308570;
6793 case CDCLK_FREQ_675_617:
6794 return 617140;
6795 default:
6796 WARN(1, "Unknown cd freq selection\n");
6797 }
6798 } else {
6799 /* vco 8100 */
6800 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6801 case CDCLK_FREQ_450_432:
6802 return 450000;
6803 case CDCLK_FREQ_337_308:
6804 return 337500;
6805 case CDCLK_FREQ_675_617:
6806 return 675000;
6807 default:
6808 WARN(1, "Unknown cd freq selection\n");
6809 }
6810 }
6811
6812 /* error case, do as if DPLL0 isn't enabled */
6813 return 24000;
6814}
6815
6816static int broxton_get_display_clock_speed(struct drm_device *dev)
6817{
6818 struct drm_i915_private *dev_priv = to_i915(dev);
6819 uint32_t cdctl = I915_READ(CDCLK_CTL);
6820 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6821 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6822 int cdclk;
6823
6824 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6825 return 19200;
6826
6827 cdclk = 19200 * pll_ratio / 2;
6828
6829 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6830 case BXT_CDCLK_CD2X_DIV_SEL_1:
6831 return cdclk; /* 576MHz or 624MHz */
6832 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6833 return cdclk * 2 / 3; /* 384MHz */
6834 case BXT_CDCLK_CD2X_DIV_SEL_2:
6835 return cdclk / 2; /* 288MHz */
6836 case BXT_CDCLK_CD2X_DIV_SEL_4:
6837 return cdclk / 4; /* 144MHz */
6838 }
6839
6840 /* error case, do as if DE PLL isn't enabled */
6841 return 19200;
6842}
6843
6844static int broadwell_get_display_clock_speed(struct drm_device *dev)
6845{
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 uint32_t lcpll = I915_READ(LCPLL_CTL);
6848 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6849
6850 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6851 return 800000;
6852 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6853 return 450000;
6854 else if (freq == LCPLL_CLK_FREQ_450)
6855 return 450000;
6856 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6857 return 540000;
6858 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6859 return 337500;
6860 else
6861 return 675000;
6862}
6863
6864static int haswell_get_display_clock_speed(struct drm_device *dev)
6865{
6866 struct drm_i915_private *dev_priv = dev->dev_private;
6867 uint32_t lcpll = I915_READ(LCPLL_CTL);
6868 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6869
6870 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6871 return 800000;
6872 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6873 return 450000;
6874 else if (freq == LCPLL_CLK_FREQ_450)
6875 return 450000;
6876 else if (IS_HSW_ULT(dev))
6877 return 337500;
6878 else
6879 return 540000;
6880}
6881
6882static int valleyview_get_display_clock_speed(struct drm_device *dev)
6883{
6884 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6885 CCK_DISPLAY_CLOCK_CONTROL);
6886}
6887
6888static int ilk_get_display_clock_speed(struct drm_device *dev)
6889{
6890 return 450000;
6891}
6892
6893static int i945_get_display_clock_speed(struct drm_device *dev)
6894{
6895 return 400000;
6896}
6897
6898static int i915_get_display_clock_speed(struct drm_device *dev)
6899{
6900 return 333333;
6901}
6902
6903static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6904{
6905 return 200000;
6906}
6907
6908static int pnv_get_display_clock_speed(struct drm_device *dev)
6909{
6910 u16 gcfgc = 0;
6911
6912 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6913
6914 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6915 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6916 return 266667;
6917 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6918 return 333333;
6919 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6920 return 444444;
6921 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6922 return 200000;
6923 default:
6924 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6925 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6926 return 133333;
6927 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6928 return 166667;
6929 }
6930}
6931
6932static int i915gm_get_display_clock_speed(struct drm_device *dev)
6933{
6934 u16 gcfgc = 0;
6935
6936 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6937
6938 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6939 return 133333;
6940 else {
6941 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6942 case GC_DISPLAY_CLOCK_333_MHZ:
6943 return 333333;
6944 default:
6945 case GC_DISPLAY_CLOCK_190_200_MHZ:
6946 return 190000;
6947 }
6948 }
6949}
6950
6951static int i865_get_display_clock_speed(struct drm_device *dev)
6952{
6953 return 266667;
6954}
6955
6956static int i85x_get_display_clock_speed(struct drm_device *dev)
6957{
6958 u16 hpllcc = 0;
6959
6960 /*
6961 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6962 * encoding is different :(
6963 * FIXME is this the right way to detect 852GM/852GMV?
6964 */
6965 if (dev->pdev->revision == 0x1)
6966 return 133333;
6967
6968 pci_bus_read_config_word(dev->pdev->bus,
6969 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6970
6971 /* Assume that the hardware is in the high speed state. This
6972 * should be the default.
6973 */
6974 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6975 case GC_CLOCK_133_200:
6976 case GC_CLOCK_133_200_2:
6977 case GC_CLOCK_100_200:
6978 return 200000;
6979 case GC_CLOCK_166_250:
6980 return 250000;
6981 case GC_CLOCK_100_133:
6982 return 133333;
6983 case GC_CLOCK_133_266:
6984 case GC_CLOCK_133_266_2:
6985 case GC_CLOCK_166_266:
6986 return 266667;
6987 }
6988
6989 /* Shouldn't happen */
6990 return 0;
6991}
6992
6993static int i830_get_display_clock_speed(struct drm_device *dev)
6994{
6995 return 133333;
6996}
6997
6998static unsigned int intel_hpll_vco(struct drm_device *dev)
6999{
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7001 static const unsigned int blb_vco[8] = {
7002 [0] = 3200000,
7003 [1] = 4000000,
7004 [2] = 5333333,
7005 [3] = 4800000,
7006 [4] = 6400000,
7007 };
7008 static const unsigned int pnv_vco[8] = {
7009 [0] = 3200000,
7010 [1] = 4000000,
7011 [2] = 5333333,
7012 [3] = 4800000,
7013 [4] = 2666667,
7014 };
7015 static const unsigned int cl_vco[8] = {
7016 [0] = 3200000,
7017 [1] = 4000000,
7018 [2] = 5333333,
7019 [3] = 6400000,
7020 [4] = 3333333,
7021 [5] = 3566667,
7022 [6] = 4266667,
7023 };
7024 static const unsigned int elk_vco[8] = {
7025 [0] = 3200000,
7026 [1] = 4000000,
7027 [2] = 5333333,
7028 [3] = 4800000,
7029 };
7030 static const unsigned int ctg_vco[8] = {
7031 [0] = 3200000,
7032 [1] = 4000000,
7033 [2] = 5333333,
7034 [3] = 6400000,
7035 [4] = 2666667,
7036 [5] = 4266667,
7037 };
7038 const unsigned int *vco_table;
7039 unsigned int vco;
7040 uint8_t tmp = 0;
7041
7042 /* FIXME other chipsets? */
7043 if (IS_GM45(dev))
7044 vco_table = ctg_vco;
7045 else if (IS_G4X(dev))
7046 vco_table = elk_vco;
7047 else if (IS_CRESTLINE(dev))
7048 vco_table = cl_vco;
7049 else if (IS_PINEVIEW(dev))
7050 vco_table = pnv_vco;
7051 else if (IS_G33(dev))
7052 vco_table = blb_vco;
7053 else
7054 return 0;
7055
7056 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7057
7058 vco = vco_table[tmp & 0x7];
7059 if (vco == 0)
7060 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7061 else
7062 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7063
7064 return vco;
7065}
7066
7067static int gm45_get_display_clock_speed(struct drm_device *dev)
7068{
7069 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7070 uint16_t tmp = 0;
7071
7072 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7073
7074 cdclk_sel = (tmp >> 12) & 0x1;
7075
7076 switch (vco) {
7077 case 2666667:
7078 case 4000000:
7079 case 5333333:
7080 return cdclk_sel ? 333333 : 222222;
7081 case 3200000:
7082 return cdclk_sel ? 320000 : 228571;
7083 default:
7084 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7085 return 222222;
7086 }
7087}
7088
7089static int i965gm_get_display_clock_speed(struct drm_device *dev)
7090{
7091 static const uint8_t div_3200[] = { 16, 10, 8 };
7092 static const uint8_t div_4000[] = { 20, 12, 10 };
7093 static const uint8_t div_5333[] = { 24, 16, 14 };
7094 const uint8_t *div_table;
7095 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7096 uint16_t tmp = 0;
7097
7098 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7099
7100 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7101
7102 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7103 goto fail;
7104
7105 switch (vco) {
7106 case 3200000:
7107 div_table = div_3200;
7108 break;
7109 case 4000000:
7110 div_table = div_4000;
7111 break;
7112 case 5333333:
7113 div_table = div_5333;
7114 break;
7115 default:
7116 goto fail;
7117 }
7118
7119 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7120
7121fail:
7122 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7123 return 200000;
7124}
7125
7126static int g33_get_display_clock_speed(struct drm_device *dev)
7127{
7128 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7129 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7130 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7131 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7132 const uint8_t *div_table;
7133 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7134 uint16_t tmp = 0;
7135
7136 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7137
7138 cdclk_sel = (tmp >> 4) & 0x7;
7139
7140 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7141 goto fail;
7142
7143 switch (vco) {
7144 case 3200000:
7145 div_table = div_3200;
7146 break;
7147 case 4000000:
7148 div_table = div_4000;
7149 break;
7150 case 4800000:
7151 div_table = div_4800;
7152 break;
7153 case 5333333:
7154 div_table = div_5333;
7155 break;
7156 default:
7157 goto fail;
7158 }
7159
7160 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7161
7162fail:
7163 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7164 return 190476;
7165}
7166
7167static void
7168intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7169{
7170 while (*num > DATA_LINK_M_N_MASK ||
7171 *den > DATA_LINK_M_N_MASK) {
7172 *num >>= 1;
7173 *den >>= 1;
7174 }
7175}
7176
7177static void compute_m_n(unsigned int m, unsigned int n,
7178 uint32_t *ret_m, uint32_t *ret_n)
7179{
7180 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7181 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7182 intel_reduce_m_n_ratio(ret_m, ret_n);
7183}
7184
7185void
7186intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7187 int pixel_clock, int link_clock,
7188 struct intel_link_m_n *m_n)
7189{
7190 m_n->tu = 64;
7191
7192 compute_m_n(bits_per_pixel * pixel_clock,
7193 link_clock * nlanes * 8,
7194 &m_n->gmch_m, &m_n->gmch_n);
7195
7196 compute_m_n(pixel_clock, link_clock,
7197 &m_n->link_m, &m_n->link_n);
7198}
7199
7200static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7201{
7202 if (i915.panel_use_ssc >= 0)
7203 return i915.panel_use_ssc != 0;
7204 return dev_priv->vbt.lvds_use_ssc
7205 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7206}
7207
7208static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7209 int num_connectors)
7210{
7211 struct drm_device *dev = crtc_state->base.crtc->dev;
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213 int refclk;
7214
7215 WARN_ON(!crtc_state->base.state);
7216
7217 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7218 refclk = 100000;
7219 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7220 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7221 refclk = dev_priv->vbt.lvds_ssc_freq;
7222 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7223 } else if (!IS_GEN2(dev)) {
7224 refclk = 96000;
7225 } else {
7226 refclk = 48000;
7227 }
7228
7229 return refclk;
7230}
7231
7232static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7233{
7234 return (1 << dpll->n) << 16 | dpll->m2;
7235}
7236
7237static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7238{
7239 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7240}
7241
7242static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7243 struct intel_crtc_state *crtc_state,
7244 intel_clock_t *reduced_clock)
7245{
7246 struct drm_device *dev = crtc->base.dev;
7247 u32 fp, fp2 = 0;
7248
7249 if (IS_PINEVIEW(dev)) {
7250 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7251 if (reduced_clock)
7252 fp2 = pnv_dpll_compute_fp(reduced_clock);
7253 } else {
7254 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7255 if (reduced_clock)
7256 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7257 }
7258
7259 crtc_state->dpll_hw_state.fp0 = fp;
7260
7261 crtc->lowfreq_avail = false;
7262 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7263 reduced_clock) {
7264 crtc_state->dpll_hw_state.fp1 = fp2;
7265 crtc->lowfreq_avail = true;
7266 } else {
7267 crtc_state->dpll_hw_state.fp1 = fp;
7268 }
7269}
7270
7271static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum i915_pipe
7272 pipe)
7273{
7274 u32 reg_val;
7275
7276 /*
7277 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7278 * and set it to a reasonable value instead.
7279 */
7280 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7281 reg_val &= 0xffffff00;
7282 reg_val |= 0x00000030;
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7284
7285 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7286 reg_val &= 0x8cffffff;
7287 reg_val = 0x8c000000;
7288 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7289
7290 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7291 reg_val &= 0xffffff00;
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7293
7294 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7295 reg_val &= 0x00ffffff;
7296 reg_val |= 0xb0000000;
7297 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7298}
7299
7300static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7301 struct intel_link_m_n *m_n)
7302{
7303 struct drm_device *dev = crtc->base.dev;
7304 struct drm_i915_private *dev_priv = dev->dev_private;
7305 int pipe = crtc->pipe;
7306
7307 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7308 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7309 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7310 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7311}
7312
7313static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7314 struct intel_link_m_n *m_n,
7315 struct intel_link_m_n *m2_n2)
7316{
7317 struct drm_device *dev = crtc->base.dev;
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319 int pipe = crtc->pipe;
7320 enum transcoder transcoder = crtc->config->cpu_transcoder;
7321
7322 if (INTEL_INFO(dev)->gen >= 5) {
7323 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7324 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7325 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7326 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7327 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7328 * for gen < 8) and if DRRS is supported (to make sure the
7329 * registers are not unnecessarily accessed).
7330 */
7331 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7332 crtc->config->has_drrs) {
7333 I915_WRITE(PIPE_DATA_M2(transcoder),
7334 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7335 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7336 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7337 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7338 }
7339 } else {
7340 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7341 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7342 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7343 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7344 }
7345}
7346
7347void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7348{
7349 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7350
7351 if (m_n == M1_N1) {
7352 dp_m_n = &crtc->config->dp_m_n;
7353 dp_m2_n2 = &crtc->config->dp_m2_n2;
7354 } else if (m_n == M2_N2) {
7355
7356 /*
7357 * M2_N2 registers are not supported. Hence m2_n2 divider value
7358 * needs to be programmed into M1_N1.
7359 */
7360 dp_m_n = &crtc->config->dp_m2_n2;
7361 } else {
7362 DRM_ERROR("Unsupported divider value\n");
7363 return;
7364 }
7365
7366 if (crtc->config->has_pch_encoder)
7367 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7368 else
7369 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7370}
7371
7372static void vlv_compute_dpll(struct intel_crtc *crtc,
7373 struct intel_crtc_state *pipe_config)
7374{
7375 u32 dpll, dpll_md;
7376
7377 /*
7378 * Enable DPIO clock input. We should never disable the reference
7379 * clock for pipe B, since VGA hotplug / manual detection depends
7380 * on it.
7381 */
7382 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7383 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7384 /* We should never disable this, set it here for state tracking */
7385 if (crtc->pipe == PIPE_B)
7386 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7387 dpll |= DPLL_VCO_ENABLE;
7388 pipe_config->dpll_hw_state.dpll = dpll;
7389
7390 dpll_md = (pipe_config->pixel_multiplier - 1)
7391 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7392 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7393}
7394
7395static void vlv_prepare_pll(struct intel_crtc *crtc,
7396 const struct intel_crtc_state *pipe_config)
7397{
7398 struct drm_device *dev = crtc->base.dev;
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400 int pipe = crtc->pipe;
7401 u32 mdiv;
7402 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7403 u32 coreclk, reg_val;
7404
7405 mutex_lock(&dev_priv->sb_lock);
7406
7407 bestn = pipe_config->dpll.n;
7408 bestm1 = pipe_config->dpll.m1;
7409 bestm2 = pipe_config->dpll.m2;
7410 bestp1 = pipe_config->dpll.p1;
7411 bestp2 = pipe_config->dpll.p2;
7412
7413 /* See eDP HDMI DPIO driver vbios notes doc */
7414
7415 /* PLL B needs special handling */
7416 if (pipe == PIPE_B)
7417 vlv_pllb_recal_opamp(dev_priv, pipe);
7418
7419 /* Set up Tx target for periodic Rcomp update */
7420 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7421
7422 /* Disable target IRef on PLL */
7423 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7424 reg_val &= 0x00ffffff;
7425 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7426
7427 /* Disable fast lock */
7428 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7429
7430 /* Set idtafcrecal before PLL is enabled */
7431 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7432 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7433 mdiv |= ((bestn << DPIO_N_SHIFT));
7434 mdiv |= (1 << DPIO_K_SHIFT);
7435
7436 /*
7437 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7438 * but we don't support that).
7439 * Note: don't use the DAC post divider as it seems unstable.
7440 */
7441 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7442 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7443
7444 mdiv |= DPIO_ENABLE_CALIBRATION;
7445 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7446
7447 /* Set HBR and RBR LPF coefficients */
7448 if (pipe_config->port_clock == 162000 ||
7449 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7450 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7451 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7452 0x009f0003);
7453 else
7454 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7455 0x00d0000f);
7456
7457 if (pipe_config->has_dp_encoder) {
7458 /* Use SSC source */
7459 if (pipe == PIPE_A)
7460 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7461 0x0df40000);
7462 else
7463 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7464 0x0df70000);
7465 } else { /* HDMI or VGA */
7466 /* Use bend source */
7467 if (pipe == PIPE_A)
7468 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7469 0x0df70000);
7470 else
7471 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7472 0x0df40000);
7473 }
7474
7475 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7476 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7477 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7478 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7479 coreclk |= 0x01000000;
7480 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7481
7482 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7483 mutex_unlock(&dev_priv->sb_lock);
7484}
7485
7486static void chv_compute_dpll(struct intel_crtc *crtc,
7487 struct intel_crtc_state *pipe_config)
7488{
7489 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7490 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7491 DPLL_VCO_ENABLE;
7492 if (crtc->pipe != PIPE_A)
7493 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7494
7495 pipe_config->dpll_hw_state.dpll_md =
7496 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7497}
7498
7499static void chv_prepare_pll(struct intel_crtc *crtc,
7500 const struct intel_crtc_state *pipe_config)
7501{
7502 struct drm_device *dev = crtc->base.dev;
7503 struct drm_i915_private *dev_priv = dev->dev_private;
7504 int pipe = crtc->pipe;
7505 int dpll_reg = DPLL(crtc->pipe);
7506 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7507 u32 loopfilter, tribuf_calcntr;
7508 u32 bestn __unused, bestm1 __unused, bestm2, bestp1, bestp2, bestm2_frac;
7509 u32 dpio_val;
7510 int vco;
7511
7512 bestn = pipe_config->dpll.n;
7513 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7514 bestm1 = pipe_config->dpll.m1;
7515 bestm2 = pipe_config->dpll.m2 >> 22;
7516 bestp1 = pipe_config->dpll.p1;
7517 bestp2 = pipe_config->dpll.p2;
7518 vco = pipe_config->dpll.vco;
7519 dpio_val = 0;
7520 loopfilter = 0;
7521
7522 /*
7523 * Enable Refclk and SSC
7524 */
7525 I915_WRITE(dpll_reg,
7526 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7527
7528 mutex_lock(&dev_priv->sb_lock);
7529
7530 /* p1 and p2 divider */
7531 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7532 5 << DPIO_CHV_S1_DIV_SHIFT |
7533 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7534 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7535 1 << DPIO_CHV_K_DIV_SHIFT);
7536
7537 /* Feedback post-divider - m2 */
7538 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7539
7540 /* Feedback refclk divider - n and m1 */
7541 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7542 DPIO_CHV_M1_DIV_BY_2 |
7543 1 << DPIO_CHV_N_DIV_SHIFT);
7544
7545 /* M2 fraction division */
7546 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7547
7548 /* M2 fraction division enable */
7549 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7550 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7551 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7552 if (bestm2_frac)
7553 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7554 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7555
7556 /* Program digital lock detect threshold */
7557 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7558 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7559 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7560 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7561 if (!bestm2_frac)
7562 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7563 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7564
7565 /* Loop filter */
7566 if (vco == 5400000) {
7567 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7568 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7569 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7570 tribuf_calcntr = 0x9;
7571 } else if (vco <= 6200000) {
7572 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7573 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7574 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7575 tribuf_calcntr = 0x9;
7576 } else if (vco <= 6480000) {
7577 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7578 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7579 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7580 tribuf_calcntr = 0x8;
7581 } else {
7582 /* Not supported. Apply the same limits as in the max case */
7583 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7584 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7585 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7586 tribuf_calcntr = 0;
7587 }
7588 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7589
7590 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7591 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7592 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7593 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7594
7595 /* AFC Recal */
7596 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7597 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7598 DPIO_AFC_RECAL);
7599
7600 mutex_unlock(&dev_priv->sb_lock);
7601}
7602
7603/**
7604 * vlv_force_pll_on - forcibly enable just the PLL
7605 * @dev_priv: i915 private structure
7606 * @pipe: pipe PLL to enable
7607 * @dpll: PLL configuration
7608 *
7609 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7610 * in cases where we need the PLL enabled even when @pipe is not going to
7611 * be enabled.
7612 */
7613void vlv_force_pll_on(struct drm_device *dev, enum i915_pipe pipe,
7614 const struct dpll *dpll)
7615{
7616 struct intel_crtc *crtc =
7617 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7618 struct intel_crtc_state pipe_config = {
7619 .base.crtc = &crtc->base,
7620 .pixel_multiplier = 1,
7621 .dpll = *dpll,
7622 };
7623
7624 if (IS_CHERRYVIEW(dev)) {
7625 chv_compute_dpll(crtc, &pipe_config);
7626 chv_prepare_pll(crtc, &pipe_config);
7627 chv_enable_pll(crtc, &pipe_config);
7628 } else {
7629 vlv_compute_dpll(crtc, &pipe_config);
7630 vlv_prepare_pll(crtc, &pipe_config);
7631 vlv_enable_pll(crtc, &pipe_config);
7632 }
7633}
7634
7635/**
7636 * vlv_force_pll_off - forcibly disable just the PLL
7637 * @dev_priv: i915 private structure
7638 * @pipe: pipe PLL to disable
7639 *
7640 * Disable the PLL for @pipe. To be used in cases where we need
7641 * the PLL enabled even when @pipe is not going to be enabled.
7642 */
7643void vlv_force_pll_off(struct drm_device *dev, enum i915_pipe pipe)
7644{
7645 if (IS_CHERRYVIEW(dev))
7646 chv_disable_pll(to_i915(dev), pipe);
7647 else
7648 vlv_disable_pll(to_i915(dev), pipe);
7649}
7650
7651static void i9xx_compute_dpll(struct intel_crtc *crtc,
7652 struct intel_crtc_state *crtc_state,
7653 intel_clock_t *reduced_clock,
7654 int num_connectors)
7655{
7656 struct drm_device *dev = crtc->base.dev;
7657 struct drm_i915_private *dev_priv = dev->dev_private;
7658 u32 dpll;
7659 bool is_sdvo;
7660 struct dpll *clock = &crtc_state->dpll;
7661
7662 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7663
7664 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7665 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7666
7667 dpll = DPLL_VGA_MODE_DIS;
7668
7669 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7670 dpll |= DPLLB_MODE_LVDS;
7671 else
7672 dpll |= DPLLB_MODE_DAC_SERIAL;
7673
7674 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7675 dpll |= (crtc_state->pixel_multiplier - 1)
7676 << SDVO_MULTIPLIER_SHIFT_HIRES;
7677 }
7678
7679 if (is_sdvo)
7680 dpll |= DPLL_SDVO_HIGH_SPEED;
7681
7682 if (crtc_state->has_dp_encoder)
7683 dpll |= DPLL_SDVO_HIGH_SPEED;
7684
7685 /* compute bitmask from p1 value */
7686 if (IS_PINEVIEW(dev))
7687 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7688 else {
7689 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7690 if (IS_G4X(dev) && reduced_clock)
7691 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7692 }
7693 switch (clock->p2) {
7694 case 5:
7695 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7696 break;
7697 case 7:
7698 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7699 break;
7700 case 10:
7701 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7702 break;
7703 case 14:
7704 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7705 break;
7706 }
7707 if (INTEL_INFO(dev)->gen >= 4)
7708 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7709
7710 if (crtc_state->sdvo_tv_clock)
7711 dpll |= PLL_REF_INPUT_TVCLKINBC;
7712 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7713 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7714 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7715 else
7716 dpll |= PLL_REF_INPUT_DREFCLK;
7717
7718 dpll |= DPLL_VCO_ENABLE;
7719 crtc_state->dpll_hw_state.dpll = dpll;
7720
7721 if (INTEL_INFO(dev)->gen >= 4) {
7722 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7723 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7724 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7725 }
7726}
7727
7728static void i8xx_compute_dpll(struct intel_crtc *crtc,
7729 struct intel_crtc_state *crtc_state,
7730 intel_clock_t *reduced_clock,
7731 int num_connectors)
7732{
7733 struct drm_device *dev = crtc->base.dev;
7734 struct drm_i915_private *dev_priv = dev->dev_private;
7735 u32 dpll;
7736 struct dpll *clock = &crtc_state->dpll;
7737
7738 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7739
7740 dpll = DPLL_VGA_MODE_DIS;
7741
7742 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7743 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7744 } else {
7745 if (clock->p1 == 2)
7746 dpll |= PLL_P1_DIVIDE_BY_TWO;
7747 else
7748 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7749 if (clock->p2 == 4)
7750 dpll |= PLL_P2_DIVIDE_BY_4;
7751 }
7752
7753 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7754 dpll |= DPLL_DVO_2X_MODE;
7755
7756 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7757 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7758 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7759 else
7760 dpll |= PLL_REF_INPUT_DREFCLK;
7761
7762 dpll |= DPLL_VCO_ENABLE;
7763 crtc_state->dpll_hw_state.dpll = dpll;
7764}
7765
7766static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7767{
7768 struct drm_device *dev = intel_crtc->base.dev;
7769 struct drm_i915_private *dev_priv = dev->dev_private;
7770 enum i915_pipe pipe = intel_crtc->pipe;
7771 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7772 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7773 uint32_t crtc_vtotal, crtc_vblank_end;
7774 int vsyncshift = 0;
7775
7776 /* We need to be careful not to changed the adjusted mode, for otherwise
7777 * the hw state checker will get angry at the mismatch. */
7778 crtc_vtotal = adjusted_mode->crtc_vtotal;
7779 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7780
7781 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7782 /* the chip adds 2 halflines automatically */
7783 crtc_vtotal -= 1;
7784 crtc_vblank_end -= 1;
7785
7786 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7787 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7788 else
7789 vsyncshift = adjusted_mode->crtc_hsync_start -
7790 adjusted_mode->crtc_htotal / 2;
7791 if (vsyncshift < 0)
7792 vsyncshift += adjusted_mode->crtc_htotal;
7793 }
7794
7795 if (INTEL_INFO(dev)->gen > 3)
7796 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7797
7798 I915_WRITE(HTOTAL(cpu_transcoder),
7799 (adjusted_mode->crtc_hdisplay - 1) |
7800 ((adjusted_mode->crtc_htotal - 1) << 16));
7801 I915_WRITE(HBLANK(cpu_transcoder),
7802 (adjusted_mode->crtc_hblank_start - 1) |
7803 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7804 I915_WRITE(HSYNC(cpu_transcoder),
7805 (adjusted_mode->crtc_hsync_start - 1) |
7806 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7807
7808 I915_WRITE(VTOTAL(cpu_transcoder),
7809 (adjusted_mode->crtc_vdisplay - 1) |
7810 ((crtc_vtotal - 1) << 16));
7811 I915_WRITE(VBLANK(cpu_transcoder),
7812 (adjusted_mode->crtc_vblank_start - 1) |
7813 ((crtc_vblank_end - 1) << 16));
7814 I915_WRITE(VSYNC(cpu_transcoder),
7815 (adjusted_mode->crtc_vsync_start - 1) |
7816 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7817
7818 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7819 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7820 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7821 * bits. */
7822 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7823 (pipe == PIPE_B || pipe == PIPE_C))
7824 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7825
7826 /* pipesrc controls the size that is scaled from, which should
7827 * always be the user's requested size.
7828 */
7829 I915_WRITE(PIPESRC(pipe),
7830 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7831 (intel_crtc->config->pipe_src_h - 1));
7832}
7833
7834static void intel_get_pipe_timings(struct intel_crtc *crtc,
7835 struct intel_crtc_state *pipe_config)
7836{
7837 struct drm_device *dev = crtc->base.dev;
7838 struct drm_i915_private *dev_priv = dev->dev_private;
7839 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7840 uint32_t tmp;
7841
7842 tmp = I915_READ(HTOTAL(cpu_transcoder));
7843 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7844 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7845 tmp = I915_READ(HBLANK(cpu_transcoder));
7846 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7847 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7848 tmp = I915_READ(HSYNC(cpu_transcoder));
7849 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7850 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7851
7852 tmp = I915_READ(VTOTAL(cpu_transcoder));
7853 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7854 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7855 tmp = I915_READ(VBLANK(cpu_transcoder));
7856 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7857 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7858 tmp = I915_READ(VSYNC(cpu_transcoder));
7859 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7860 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7861
7862 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7863 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7864 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7865 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7866 }
7867
7868 tmp = I915_READ(PIPESRC(crtc->pipe));
7869 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7870 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7871
7872 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7873 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7874}
7875
7876void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7877 struct intel_crtc_state *pipe_config)
7878{
7879 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7880 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7881 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7882 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7883
7884 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7885 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7886 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7887 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7888
7889 mode->flags = pipe_config->base.adjusted_mode.flags;
7890 mode->type = DRM_MODE_TYPE_DRIVER;
7891
7892 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7893 mode->flags |= pipe_config->base.adjusted_mode.flags;
7894
7895 mode->hsync = drm_mode_hsync(mode);
7896 mode->vrefresh = drm_mode_vrefresh(mode);
7897 drm_mode_set_name(mode);
7898}
7899
7900static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7901{
7902 struct drm_device *dev = intel_crtc->base.dev;
7903 struct drm_i915_private *dev_priv = dev->dev_private;
7904 uint32_t pipeconf;
7905
7906 pipeconf = 0;
7907
7908 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7909 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7910 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7911
7912 if (intel_crtc->config->double_wide)
7913 pipeconf |= PIPECONF_DOUBLE_WIDE;
7914
7915 /* only g4x and later have fancy bpc/dither controls */
7916 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7917 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7918 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7919 pipeconf |= PIPECONF_DITHER_EN |
7920 PIPECONF_DITHER_TYPE_SP;
7921
7922 switch (intel_crtc->config->pipe_bpp) {
7923 case 18:
7924 pipeconf |= PIPECONF_6BPC;
7925 break;
7926 case 24:
7927 pipeconf |= PIPECONF_8BPC;
7928 break;
7929 case 30:
7930 pipeconf |= PIPECONF_10BPC;
7931 break;
7932 default:
7933 /* Case prevented by intel_choose_pipe_bpp_dither. */
7934 BUG();
7935 }
7936 }
7937
7938 if (HAS_PIPE_CXSR(dev)) {
7939 if (intel_crtc->lowfreq_avail) {
7940 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7941 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7942 } else {
7943 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7944 }
7945 }
7946
7947 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7948 if (INTEL_INFO(dev)->gen < 4 ||
7949 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7950 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7951 else
7952 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7953 } else
7954 pipeconf |= PIPECONF_PROGRESSIVE;
7955
7956 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7957 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7958
7959 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7960 POSTING_READ(PIPECONF(intel_crtc->pipe));
7961}
7962
7963static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7964 struct intel_crtc_state *crtc_state)
7965{
7966 struct drm_device *dev = crtc->base.dev;
7967 struct drm_i915_private *dev_priv = dev->dev_private;
7968 int refclk, num_connectors = 0;
7969 intel_clock_t clock;
7970 bool ok;
7971 bool is_dsi = false;
7972 struct intel_encoder *encoder;
7973 const intel_limit_t *limit;
7974 struct drm_atomic_state *state = crtc_state->base.state;
7975 struct drm_connector *connector;
7976 struct drm_connector_state *connector_state;
7977 int i;
7978
7979 memset(&crtc_state->dpll_hw_state, 0,
7980 sizeof(crtc_state->dpll_hw_state));
7981
7982 for_each_connector_in_state(state, connector, connector_state, i) {
7983 if (connector_state->crtc != &crtc->base)
7984 continue;
7985
7986 encoder = to_intel_encoder(connector_state->best_encoder);
7987
7988 switch (encoder->type) {
7989 case INTEL_OUTPUT_DSI:
7990 is_dsi = true;
7991 break;
7992 default:
7993 break;
7994 }
7995
7996 num_connectors++;
7997 }
7998
7999 if (is_dsi)
8000 return 0;
8001
8002 if (!crtc_state->clock_set) {
8003 refclk = i9xx_get_refclk(crtc_state, num_connectors);
8004
8005 /*
8006 * Returns a set of divisors for the desired target clock with
8007 * the given refclk, or FALSE. The returned values represent
8008 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
8009 * 2) / p1 / p2.
8010 */
8011 limit = intel_limit(crtc_state, refclk);
8012 ok = dev_priv->display.find_dpll(limit, crtc_state,
8013 crtc_state->port_clock,
8014 refclk, NULL, &clock);
8015 if (!ok) {
8016 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8017 return -EINVAL;
8018 }
8019
8020 /* Compat-code for transition, will disappear. */
8021 crtc_state->dpll.n = clock.n;
8022 crtc_state->dpll.m1 = clock.m1;
8023 crtc_state->dpll.m2 = clock.m2;
8024 crtc_state->dpll.p1 = clock.p1;
8025 crtc_state->dpll.p2 = clock.p2;
8026 }
8027
8028 if (IS_GEN2(dev)) {
8029 i8xx_compute_dpll(crtc, crtc_state, NULL,
8030 num_connectors);
8031 } else if (IS_CHERRYVIEW(dev)) {
8032 chv_compute_dpll(crtc, crtc_state);
8033 } else if (IS_VALLEYVIEW(dev)) {
8034 vlv_compute_dpll(crtc, crtc_state);
8035 } else {
8036 i9xx_compute_dpll(crtc, crtc_state, NULL,
8037 num_connectors);
8038 }
8039
8040 return 0;
8041}
8042
8043static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8044 struct intel_crtc_state *pipe_config)
8045{
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 uint32_t tmp;
8049
8050 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8051 return;
8052
8053 tmp = I915_READ(PFIT_CONTROL);
8054 if (!(tmp & PFIT_ENABLE))
8055 return;
8056
8057 /* Check whether the pfit is attached to our pipe. */
8058 if (INTEL_INFO(dev)->gen < 4) {
8059 if (crtc->pipe != PIPE_B)
8060 return;
8061 } else {
8062 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8063 return;
8064 }
8065
8066 pipe_config->gmch_pfit.control = tmp;
8067 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8068 if (INTEL_INFO(dev)->gen < 5)
8069 pipe_config->gmch_pfit.lvds_border_bits =
8070 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8071}
8072
8073static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8074 struct intel_crtc_state *pipe_config)
8075{
8076 struct drm_device *dev = crtc->base.dev;
8077 struct drm_i915_private *dev_priv = dev->dev_private;
8078 int pipe = pipe_config->cpu_transcoder;
8079 intel_clock_t clock;
8080 u32 mdiv;
8081 int refclk = 100000;
8082
8083 /* In case of MIPI DPLL will not even be used */
8084 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8085 return;
8086
8087 mutex_lock(&dev_priv->sb_lock);
8088 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8089 mutex_unlock(&dev_priv->sb_lock);
8090
8091 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8092 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8093 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8094 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8095 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8096
8097 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8098}
8099
8100static void
8101i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8102 struct intel_initial_plane_config *plane_config)
8103{
8104 struct drm_device *dev = crtc->base.dev;
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8106 u32 val, base;
8107 int pipe = crtc->pipe, plane = crtc->plane;
8108 int fourcc, pixel_format;
8109 unsigned int aligned_height;
8110 struct drm_framebuffer *fb;
8111 struct intel_framebuffer *intel_fb;
8112
8113 val = I915_READ(DSPCNTR(plane));
8114 if (!(val & DISPLAY_PLANE_ENABLE))
8115 return;
8116
8117 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8118 if (!intel_fb) {
8119 DRM_DEBUG_KMS("failed to alloc fb\n");
8120 return;
8121 }
8122
8123 fb = &intel_fb->base;
8124
8125 if (INTEL_INFO(dev)->gen >= 4) {
8126 if (val & DISPPLANE_TILED) {
8127 plane_config->tiling = I915_TILING_X;
8128 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8129 }
8130 }
8131
8132 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8133 fourcc = i9xx_format_to_fourcc(pixel_format);
8134 fb->pixel_format = fourcc;
8135 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8136
8137 if (INTEL_INFO(dev)->gen >= 4) {
8138 if (plane_config->tiling)
8139 (void)I915_READ(DSPTILEOFF(plane));
8140 else
8141 (void)I915_READ(DSPLINOFF(plane));
8142 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8143 } else {
8144 base = I915_READ(DSPADDR(plane));
8145 }
8146 plane_config->base = base;
8147
8148 val = I915_READ(PIPESRC(pipe));
8149 fb->width = ((val >> 16) & 0xfff) + 1;
8150 fb->height = ((val >> 0) & 0xfff) + 1;
8151
8152 val = I915_READ(DSPSTRIDE(pipe));
8153 fb->pitches[0] = val & 0xffffffc0;
8154
8155 aligned_height = intel_fb_align_height(dev, fb->height,
8156 fb->pixel_format,
8157 fb->modifier[0]);
8158
8159 plane_config->size = fb->pitches[0] * aligned_height;
8160
8161 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8162 pipe_name(pipe), plane, fb->width, fb->height,
8163 fb->bits_per_pixel, base, fb->pitches[0],
8164 plane_config->size);
8165
8166 plane_config->fb = intel_fb;
8167}
8168
8169static void chv_crtc_clock_get(struct intel_crtc *crtc,
8170 struct intel_crtc_state *pipe_config)
8171{
8172 struct drm_device *dev = crtc->base.dev;
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 int pipe = pipe_config->cpu_transcoder;
8175 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8176 intel_clock_t clock;
8177 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8178 int refclk = 100000;
8179
8180 mutex_lock(&dev_priv->sb_lock);
8181 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8182 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8183 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8184 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8185 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8186 mutex_unlock(&dev_priv->sb_lock);
8187
8188 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8189 clock.m2 = (pll_dw0 & 0xff) << 22;
8190 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8191 clock.m2 |= pll_dw2 & 0x3fffff;
8192 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8193 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8194 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8195
8196 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8197}
8198
8199static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8200 struct intel_crtc_state *pipe_config)
8201{
8202 struct drm_device *dev = crtc->base.dev;
8203 struct drm_i915_private *dev_priv = dev->dev_private;
8204 uint32_t tmp;
8205
8206 if (!intel_display_power_is_enabled(dev_priv,
8207 POWER_DOMAIN_PIPE(crtc->pipe)))
8208 return false;
8209
8210 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8211 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8212
8213 tmp = I915_READ(PIPECONF(crtc->pipe));
8214 if (!(tmp & PIPECONF_ENABLE))
8215 return false;
8216
8217 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8218 switch (tmp & PIPECONF_BPC_MASK) {
8219 case PIPECONF_6BPC:
8220 pipe_config->pipe_bpp = 18;
8221 break;
8222 case PIPECONF_8BPC:
8223 pipe_config->pipe_bpp = 24;
8224 break;
8225 case PIPECONF_10BPC:
8226 pipe_config->pipe_bpp = 30;
8227 break;
8228 default:
8229 break;
8230 }
8231 }
8232
8233 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8234 pipe_config->limited_color_range = true;
8235
8236 if (INTEL_INFO(dev)->gen < 4)
8237 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8238
8239 intel_get_pipe_timings(crtc, pipe_config);
8240
8241 i9xx_get_pfit_config(crtc, pipe_config);
8242
8243 if (INTEL_INFO(dev)->gen >= 4) {
8244 tmp = I915_READ(DPLL_MD(crtc->pipe));
8245 pipe_config->pixel_multiplier =
8246 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8247 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8248 pipe_config->dpll_hw_state.dpll_md = tmp;
8249 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8250 tmp = I915_READ(DPLL(crtc->pipe));
8251 pipe_config->pixel_multiplier =
8252 ((tmp & SDVO_MULTIPLIER_MASK)
8253 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8254 } else {
8255 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8256 * port and will be fixed up in the encoder->get_config
8257 * function. */
8258 pipe_config->pixel_multiplier = 1;
8259 }
8260 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8261 if (!IS_VALLEYVIEW(dev)) {
8262 /*
8263 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8264 * on 830. Filter it out here so that we don't
8265 * report errors due to that.
8266 */
8267 if (IS_I830(dev))
8268 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8269
8270 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8271 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8272 } else {
8273 /* Mask out read-only status bits. */
8274 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8275 DPLL_PORTC_READY_MASK |
8276 DPLL_PORTB_READY_MASK);
8277 }
8278
8279 if (IS_CHERRYVIEW(dev))
8280 chv_crtc_clock_get(crtc, pipe_config);
8281 else if (IS_VALLEYVIEW(dev))
8282 vlv_crtc_clock_get(crtc, pipe_config);
8283 else
8284 i9xx_crtc_clock_get(crtc, pipe_config);
8285
8286 /*
8287 * Normally the dotclock is filled in by the encoder .get_config()
8288 * but in case the pipe is enabled w/o any ports we need a sane
8289 * default.
8290 */
8291 pipe_config->base.adjusted_mode.crtc_clock =
8292 pipe_config->port_clock / pipe_config->pixel_multiplier;
8293
8294 return true;
8295}
8296
8297static void ironlake_init_pch_refclk(struct drm_device *dev)
8298{
8299 struct drm_i915_private *dev_priv = dev->dev_private;
8300 struct intel_encoder *encoder;
8301 int i;
8302 u32 val, final;
8303 bool has_lvds = false;
8304 bool has_cpu_edp = false;
8305 bool has_panel = false;
8306 bool has_ck505 = false;
8307 bool can_ssc = false;
8308 bool using_ssc_source = false;
8309
8310 /* We need to take the global config into account */
8311 for_each_intel_encoder(dev, encoder) {
8312 switch (encoder->type) {
8313 case INTEL_OUTPUT_LVDS:
8314 has_panel = true;
8315 has_lvds = true;
8316 break;
8317 case INTEL_OUTPUT_EDP:
8318 has_panel = true;
8319 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8320 has_cpu_edp = true;
8321 break;
8322 default:
8323 break;
8324 }
8325 }
8326
8327 if (HAS_PCH_IBX(dev)) {
8328 has_ck505 = dev_priv->vbt.display_clock_mode;
8329 can_ssc = has_ck505;
8330 } else {
8331 has_ck505 = false;
8332 can_ssc = true;
8333 }
8334
8335 /* Check if any DPLLs are using the SSC source */
8336 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8337 u32 temp = I915_READ(PCH_DPLL(i));
8338
8339 if (!(temp & DPLL_VCO_ENABLE))
8340 continue;
8341
8342 if ((temp & PLL_REF_INPUT_MASK) ==
8343 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8344 using_ssc_source = true;
8345 break;
8346 }
8347 }
8348
8349 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8350 has_panel, has_lvds, has_ck505, using_ssc_source);
8351
8352 /* Ironlake: try to setup display ref clock before DPLL
8353 * enabling. This is only under driver's control after
8354 * PCH B stepping, previous chipset stepping should be
8355 * ignoring this setting.
8356 */
8357 val = I915_READ(PCH_DREF_CONTROL);
8358
8359 /* As we must carefully and slowly disable/enable each source in turn,
8360 * compute the final state we want first and check if we need to
8361 * make any changes at all.
8362 */
8363 final = val;
8364 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8365 if (has_ck505)
8366 final |= DREF_NONSPREAD_CK505_ENABLE;
8367 else
8368 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8369
8370 final &= ~DREF_SSC_SOURCE_MASK;
8371 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8372 final &= ~DREF_SSC1_ENABLE;
8373
8374 if (has_panel) {
8375 final |= DREF_SSC_SOURCE_ENABLE;
8376
8377 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8378 final |= DREF_SSC1_ENABLE;
8379
8380 if (has_cpu_edp) {
8381 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8382 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8383 else
8384 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8385 } else
8386 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8387 } else if (using_ssc_source) {
8388 final |= DREF_SSC_SOURCE_ENABLE;
8389 final |= DREF_SSC1_ENABLE;
8390 }
8391
8392 if (final == val)
8393 return;
8394
8395 /* Always enable nonspread source */
8396 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8397
8398 if (has_ck505)
8399 val |= DREF_NONSPREAD_CK505_ENABLE;
8400 else
8401 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8402
8403 if (has_panel) {
8404 val &= ~DREF_SSC_SOURCE_MASK;
8405 val |= DREF_SSC_SOURCE_ENABLE;
8406
8407 /* SSC must be turned on before enabling the CPU output */
8408 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8409 DRM_DEBUG_KMS("Using SSC on panel\n");
8410 val |= DREF_SSC1_ENABLE;
8411 } else
8412 val &= ~DREF_SSC1_ENABLE;
8413
8414 /* Get SSC going before enabling the outputs */
8415 I915_WRITE(PCH_DREF_CONTROL, val);
8416 POSTING_READ(PCH_DREF_CONTROL);
8417 udelay(200);
8418
8419 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8420
8421 /* Enable CPU source on CPU attached eDP */
8422 if (has_cpu_edp) {
8423 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8424 DRM_DEBUG_KMS("Using SSC on eDP\n");
8425 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8426 } else
8427 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8428 } else
8429 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8430
8431 I915_WRITE(PCH_DREF_CONTROL, val);
8432 POSTING_READ(PCH_DREF_CONTROL);
8433 udelay(200);
8434 } else {
8435 DRM_DEBUG_KMS("Disabling CPU source output\n");
8436
8437 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8438
8439 /* Turn off CPU output */
8440 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8441
8442 I915_WRITE(PCH_DREF_CONTROL, val);
8443 POSTING_READ(PCH_DREF_CONTROL);
8444 udelay(200);
8445
8446 if (!using_ssc_source) {
8447 DRM_DEBUG_KMS("Disabling SSC source\n");
8448
8449 /* Turn off the SSC source */
8450 val &= ~DREF_SSC_SOURCE_MASK;
8451 val |= DREF_SSC_SOURCE_DISABLE;
8452
8453 /* Turn off SSC1 */
8454 val &= ~DREF_SSC1_ENABLE;
8455
8456 I915_WRITE(PCH_DREF_CONTROL, val);
8457 POSTING_READ(PCH_DREF_CONTROL);
8458 udelay(200);
8459 }
8460 }
8461
8462 BUG_ON(val != final);
8463}
8464
8465static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8466{
8467 uint32_t tmp;
8468
8469 tmp = I915_READ(SOUTH_CHICKEN2);
8470 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8471 I915_WRITE(SOUTH_CHICKEN2, tmp);
8472
8473 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8474 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8475 DRM_ERROR("FDI mPHY reset assert timeout\n");
8476
8477 tmp = I915_READ(SOUTH_CHICKEN2);
8478 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8479 I915_WRITE(SOUTH_CHICKEN2, tmp);
8480
8481 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8482 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8483 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8484}
8485
8486/* WaMPhyProgramming:hsw */
8487static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8488{
8489 uint32_t tmp;
8490
8491 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8492 tmp &= ~(0xFF << 24);
8493 tmp |= (0x12 << 24);
8494 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8495
8496 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8497 tmp |= (1 << 11);
8498 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8499
8500 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8501 tmp |= (1 << 11);
8502 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8503
8504 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8505 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8506 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8507
8508 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8509 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8510 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8511
8512 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8513 tmp &= ~(7 << 13);
8514 tmp |= (5 << 13);
8515 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8516
8517 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8518 tmp &= ~(7 << 13);
8519 tmp |= (5 << 13);
8520 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8521
8522 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8523 tmp &= ~0xFF;
8524 tmp |= 0x1C;
8525 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8526
8527 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8528 tmp &= ~0xFF;
8529 tmp |= 0x1C;
8530 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8531
8532 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8533 tmp &= ~(0xFF << 16);
8534 tmp |= (0x1C << 16);
8535 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8536
8537 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8538 tmp &= ~(0xFF << 16);
8539 tmp |= (0x1C << 16);
8540 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8541
8542 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8543 tmp |= (1 << 27);
8544 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8545
8546 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8547 tmp |= (1 << 27);
8548 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8549
8550 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8551 tmp &= ~(0xF << 28);
8552 tmp |= (4 << 28);
8553 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8554
8555 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8556 tmp &= ~(0xF << 28);
8557 tmp |= (4 << 28);
8558 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8559}
8560
8561/* Implements 3 different sequences from BSpec chapter "Display iCLK
8562 * Programming" based on the parameters passed:
8563 * - Sequence to enable CLKOUT_DP
8564 * - Sequence to enable CLKOUT_DP without spread
8565 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8566 */
8567static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8568 bool with_fdi)
8569{
8570 struct drm_i915_private *dev_priv = dev->dev_private;
8571 uint32_t reg, tmp;
8572
8573 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8574 with_spread = true;
8575 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8576 with_fdi = false;
8577
8578 mutex_lock(&dev_priv->sb_lock);
8579
8580 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8581 tmp &= ~SBI_SSCCTL_DISABLE;
8582 tmp |= SBI_SSCCTL_PATHALT;
8583 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8584
8585 udelay(24);
8586
8587 if (with_spread) {
8588 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8589 tmp &= ~SBI_SSCCTL_PATHALT;
8590 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8591
8592 if (with_fdi) {
8593 lpt_reset_fdi_mphy(dev_priv);
8594 lpt_program_fdi_mphy(dev_priv);
8595 }
8596 }
8597
8598 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8599 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8600 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8601 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8602
8603 mutex_unlock(&dev_priv->sb_lock);
8604}
8605
8606/* Sequence to disable CLKOUT_DP */
8607static void lpt_disable_clkout_dp(struct drm_device *dev)
8608{
8609 struct drm_i915_private *dev_priv = dev->dev_private;
8610 uint32_t reg, tmp;
8611
8612 mutex_lock(&dev_priv->sb_lock);
8613
8614 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8615 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8616 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8617 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8618
8619 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8620 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8621 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8622 tmp |= SBI_SSCCTL_PATHALT;
8623 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8624 udelay(32);
8625 }
8626 tmp |= SBI_SSCCTL_DISABLE;
8627 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8628 }
8629
8630 mutex_unlock(&dev_priv->sb_lock);
8631}
8632
8633static void lpt_init_pch_refclk(struct drm_device *dev)
8634{
8635 struct intel_encoder *encoder;
8636 bool has_vga = false;
8637
8638 for_each_intel_encoder(dev, encoder) {
8639 switch (encoder->type) {
8640 case INTEL_OUTPUT_ANALOG:
8641 has_vga = true;
8642 break;
8643 default:
8644 break;
8645 }
8646 }
8647
8648 if (has_vga)
8649 lpt_enable_clkout_dp(dev, true, true);
8650 else
8651 lpt_disable_clkout_dp(dev);
8652}
8653
8654/*
8655 * Initialize reference clocks when the driver loads
8656 */
8657void intel_init_pch_refclk(struct drm_device *dev)
8658{
8659 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8660 ironlake_init_pch_refclk(dev);
8661 else if (HAS_PCH_LPT(dev))
8662 lpt_init_pch_refclk(dev);
8663}
8664
8665static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8666{
8667 struct drm_device *dev = crtc_state->base.crtc->dev;
8668 struct drm_i915_private *dev_priv = dev->dev_private;
8669 struct drm_atomic_state *state = crtc_state->base.state;
8670 struct drm_connector *connector;
8671 struct drm_connector_state *connector_state;
8672 struct intel_encoder *encoder;
8673 int num_connectors = 0, i;
8674 bool is_lvds = false;
8675
8676 for_each_connector_in_state(state, connector, connector_state, i) {
8677 if (connector_state->crtc != crtc_state->base.crtc)
8678 continue;
8679
8680 encoder = to_intel_encoder(connector_state->best_encoder);
8681
8682 switch (encoder->type) {
8683 case INTEL_OUTPUT_LVDS:
8684 is_lvds = true;
8685 break;
8686 default:
8687 break;
8688 }
8689 num_connectors++;
8690 }
8691
8692 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8693 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8694 dev_priv->vbt.lvds_ssc_freq);
8695 return dev_priv->vbt.lvds_ssc_freq;
8696 }
8697
8698 return 120000;
8699}
8700
8701static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8702{
8703 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8705 int pipe = intel_crtc->pipe;
8706 uint32_t val;
8707
8708 val = 0;
8709
8710 switch (intel_crtc->config->pipe_bpp) {
8711 case 18:
8712 val |= PIPECONF_6BPC;
8713 break;
8714 case 24:
8715 val |= PIPECONF_8BPC;
8716 break;
8717 case 30:
8718 val |= PIPECONF_10BPC;
8719 break;
8720 case 36:
8721 val |= PIPECONF_12BPC;
8722 break;
8723 default:
8724 /* Case prevented by intel_choose_pipe_bpp_dither. */
8725 BUG();
8726 }
8727
8728 if (intel_crtc->config->dither)
8729 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8730
8731 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8732 val |= PIPECONF_INTERLACED_ILK;
8733 else
8734 val |= PIPECONF_PROGRESSIVE;
8735
8736 if (intel_crtc->config->limited_color_range)
8737 val |= PIPECONF_COLOR_RANGE_SELECT;
8738
8739 I915_WRITE(PIPECONF(pipe), val);
8740 POSTING_READ(PIPECONF(pipe));
8741}
8742
8743/*
8744 * Set up the pipe CSC unit.
8745 *
8746 * Currently only full range RGB to limited range RGB conversion
8747 * is supported, but eventually this should handle various
8748 * RGB<->YCbCr scenarios as well.
8749 */
8750static void intel_set_pipe_csc(struct drm_crtc *crtc)
8751{
8752 struct drm_device *dev = crtc->dev;
8753 struct drm_i915_private *dev_priv = dev->dev_private;
8754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8755 int pipe = intel_crtc->pipe;
8756 uint16_t coeff = 0x7800; /* 1.0 */
8757
8758 /*
8759 * TODO: Check what kind of values actually come out of the pipe
8760 * with these coeff/postoff values and adjust to get the best
8761 * accuracy. Perhaps we even need to take the bpc value into
8762 * consideration.
8763 */
8764
8765 if (intel_crtc->config->limited_color_range)
8766 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8767
8768 /*
8769 * GY/GU and RY/RU should be the other way around according
8770 * to BSpec, but reality doesn't agree. Just set them up in
8771 * a way that results in the correct picture.
8772 */
8773 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8774 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8775
8776 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8777 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8778
8779 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8780 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8781
8782 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8783 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8784 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8785
8786 if (INTEL_INFO(dev)->gen > 6) {
8787 uint16_t postoff = 0;
8788
8789 if (intel_crtc->config->limited_color_range)
8790 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8791
8792 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8793 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8794 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8795
8796 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8797 } else {
8798 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8799
8800 if (intel_crtc->config->limited_color_range)
8801 mode |= CSC_BLACK_SCREEN_OFFSET;
8802
8803 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8804 }
8805}
8806
8807static void haswell_set_pipeconf(struct drm_crtc *crtc)
8808{
8809 struct drm_device *dev = crtc->dev;
8810 struct drm_i915_private *dev_priv = dev->dev_private;
8811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8812 enum i915_pipe pipe = intel_crtc->pipe;
8813 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8814 uint32_t val;
8815
8816 val = 0;
8817
8818 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8819 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8820
8821 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8822 val |= PIPECONF_INTERLACED_ILK;
8823 else
8824 val |= PIPECONF_PROGRESSIVE;
8825
8826 I915_WRITE(PIPECONF(cpu_transcoder), val);
8827 POSTING_READ(PIPECONF(cpu_transcoder));
8828
8829 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8830 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8831
8832 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8833 val = 0;
8834
8835 switch (intel_crtc->config->pipe_bpp) {
8836 case 18:
8837 val |= PIPEMISC_DITHER_6_BPC;
8838 break;
8839 case 24:
8840 val |= PIPEMISC_DITHER_8_BPC;
8841 break;
8842 case 30:
8843 val |= PIPEMISC_DITHER_10_BPC;
8844 break;
8845 case 36:
8846 val |= PIPEMISC_DITHER_12_BPC;
8847 break;
8848 default:
8849 /* Case prevented by pipe_config_set_bpp. */
8850 BUG();
8851 }
8852
8853 if (intel_crtc->config->dither)
8854 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8855
8856 I915_WRITE(PIPEMISC(pipe), val);
8857 }
8858}
8859
8860static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8861 struct intel_crtc_state *crtc_state,
8862 intel_clock_t *clock,
8863 bool *has_reduced_clock,
8864 intel_clock_t *reduced_clock)
8865{
8866 struct drm_device *dev = crtc->dev;
8867 struct drm_i915_private *dev_priv = dev->dev_private;
8868 int refclk;
8869 const intel_limit_t *limit;
8870 bool ret;
8871
8872 refclk = ironlake_get_refclk(crtc_state);
8873
8874 /*
8875 * Returns a set of divisors for the desired target clock with the given
8876 * refclk, or FALSE. The returned values represent the clock equation:
8877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8878 */
8879 limit = intel_limit(crtc_state, refclk);
8880 ret = dev_priv->display.find_dpll(limit, crtc_state,
8881 crtc_state->port_clock,
8882 refclk, NULL, clock);
8883 if (!ret)
8884 return false;
8885
8886 return true;
8887}
8888
8889int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8890{
8891 /*
8892 * Account for spread spectrum to avoid
8893 * oversubscribing the link. Max center spread
8894 * is 2.5%; use 5% for safety's sake.
8895 */
8896 u32 bps = target_clock * bpp * 21 / 20;
8897 return DIV_ROUND_UP(bps, link_bw * 8);
8898}
8899
8900static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8901{
8902 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8903}
8904
8905static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8906 struct intel_crtc_state *crtc_state,
8907 u32 *fp,
8908 intel_clock_t *reduced_clock, u32 *fp2)
8909{
8910 struct drm_crtc *crtc = &intel_crtc->base;
8911 struct drm_device *dev = crtc->dev;
8912 struct drm_i915_private *dev_priv = dev->dev_private;
8913 struct drm_atomic_state *state = crtc_state->base.state;
8914 struct drm_connector *connector;
8915 struct drm_connector_state *connector_state;
8916 struct intel_encoder *encoder;
8917 uint32_t dpll;
8918 int factor, num_connectors = 0, i;
8919 bool is_lvds = false, is_sdvo = false;
8920
8921 for_each_connector_in_state(state, connector, connector_state, i) {
8922 if (connector_state->crtc != crtc_state->base.crtc)
8923 continue;
8924
8925 encoder = to_intel_encoder(connector_state->best_encoder);
8926
8927 switch (encoder->type) {
8928 case INTEL_OUTPUT_LVDS:
8929 is_lvds = true;
8930 break;
8931 case INTEL_OUTPUT_SDVO:
8932 case INTEL_OUTPUT_HDMI:
8933 is_sdvo = true;
8934 break;
8935 default:
8936 break;
8937 }
8938
8939 num_connectors++;
8940 }
8941
8942 /* Enable autotuning of the PLL clock (if permissible) */
8943 factor = 21;
8944 if (is_lvds) {
8945 if ((intel_panel_use_ssc(dev_priv) &&
8946 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8947 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8948 factor = 25;
8949 } else if (crtc_state->sdvo_tv_clock)
8950 factor = 20;
8951
8952 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8953 *fp |= FP_CB_TUNE;
8954
8955 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8956 *fp2 |= FP_CB_TUNE;
8957
8958 dpll = 0;
8959
8960 if (is_lvds)
8961 dpll |= DPLLB_MODE_LVDS;
8962 else
8963 dpll |= DPLLB_MODE_DAC_SERIAL;
8964
8965 dpll |= (crtc_state->pixel_multiplier - 1)
8966 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8967
8968 if (is_sdvo)
8969 dpll |= DPLL_SDVO_HIGH_SPEED;
8970 if (crtc_state->has_dp_encoder)
8971 dpll |= DPLL_SDVO_HIGH_SPEED;
8972
8973 /* compute bitmask from p1 value */
8974 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8975 /* also FPA1 */
8976 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8977
8978 switch (crtc_state->dpll.p2) {
8979 case 5:
8980 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8981 break;
8982 case 7:
8983 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8984 break;
8985 case 10:
8986 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8987 break;
8988 case 14:
8989 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8990 break;
8991 }
8992
8993 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8994 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8995 else
8996 dpll |= PLL_REF_INPUT_DREFCLK;
8997
8998 return dpll | DPLL_VCO_ENABLE;
8999}
9000
9001static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9002 struct intel_crtc_state *crtc_state)
9003{
9004 struct drm_device *dev = crtc->base.dev;
9005 intel_clock_t clock, reduced_clock;
9006 u32 dpll = 0, fp = 0, fp2 = 0;
9007 bool ok, has_reduced_clock = false;
9008 bool is_lvds = false;
9009 struct intel_shared_dpll *pll;
9010
9011 memset(&crtc_state->dpll_hw_state, 0,
9012 sizeof(crtc_state->dpll_hw_state));
9013
9014 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
9015
9016 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9017 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9018
9019 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9020 &has_reduced_clock, &reduced_clock);
9021 if (!ok && !crtc_state->clock_set) {
9022 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9023 return -EINVAL;
9024 }
9025 /* Compat-code for transition, will disappear. */
9026 if (!crtc_state->clock_set) {
9027 crtc_state->dpll.n = clock.n;
9028 crtc_state->dpll.m1 = clock.m1;
9029 crtc_state->dpll.m2 = clock.m2;
9030 crtc_state->dpll.p1 = clock.p1;
9031 crtc_state->dpll.p2 = clock.p2;
9032 }
9033
9034 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9035 if (crtc_state->has_pch_encoder) {
9036 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9037 if (has_reduced_clock)
9038 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9039
9040 dpll = ironlake_compute_dpll(crtc, crtc_state,
9041 &fp, &reduced_clock,
9042 has_reduced_clock ? &fp2 : NULL);
9043
9044 crtc_state->dpll_hw_state.dpll = dpll;
9045 crtc_state->dpll_hw_state.fp0 = fp;
9046 if (has_reduced_clock)
9047 crtc_state->dpll_hw_state.fp1 = fp2;
9048 else
9049 crtc_state->dpll_hw_state.fp1 = fp;
9050
9051 pll = intel_get_shared_dpll(crtc, crtc_state);
9052 if (pll == NULL) {
9053 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9054 pipe_name(crtc->pipe));
9055 return -EINVAL;
9056 }
9057 }
9058
9059 if (is_lvds && has_reduced_clock)
9060 crtc->lowfreq_avail = true;
9061 else
9062 crtc->lowfreq_avail = false;
9063
9064 return 0;
9065}
9066
9067static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9068 struct intel_link_m_n *m_n)
9069{
9070 struct drm_device *dev = crtc->base.dev;
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 enum i915_pipe pipe = crtc->pipe;
9073
9074 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9075 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9076 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9077 & ~TU_SIZE_MASK;
9078 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9079 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9080 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9081}
9082
9083static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9084 enum transcoder transcoder,
9085 struct intel_link_m_n *m_n,
9086 struct intel_link_m_n *m2_n2)
9087{
9088 struct drm_device *dev = crtc->base.dev;
9089 struct drm_i915_private *dev_priv = dev->dev_private;
9090 enum i915_pipe pipe = crtc->pipe;
9091
9092 if (INTEL_INFO(dev)->gen >= 5) {
9093 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9094 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9095 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9096 & ~TU_SIZE_MASK;
9097 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9098 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9099 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9100 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9101 * gen < 8) and if DRRS is supported (to make sure the
9102 * registers are not unnecessarily read).
9103 */
9104 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9105 crtc->config->has_drrs) {
9106 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9107 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9108 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9109 & ~TU_SIZE_MASK;
9110 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9111 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9112 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9113 }
9114 } else {
9115 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9116 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9117 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9118 & ~TU_SIZE_MASK;
9119 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9120 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9121 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9122 }
9123}
9124
9125void intel_dp_get_m_n(struct intel_crtc *crtc,
9126 struct intel_crtc_state *pipe_config)
9127{
9128 if (pipe_config->has_pch_encoder)
9129 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9130 else
9131 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9132 &pipe_config->dp_m_n,
9133 &pipe_config->dp_m2_n2);
9134}
9135
9136static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9137 struct intel_crtc_state *pipe_config)
9138{
9139 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9140 &pipe_config->fdi_m_n, NULL);
9141}
9142
9143static void skylake_get_pfit_config(struct intel_crtc *crtc,
9144 struct intel_crtc_state *pipe_config)
9145{
9146 struct drm_device *dev = crtc->base.dev;
9147 struct drm_i915_private *dev_priv = dev->dev_private;
9148 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9149 uint32_t ps_ctrl = 0;
9150 int id = -1;
9151 int i;
9152
9153 /* find scaler attached to this pipe */
9154 for (i = 0; i < crtc->num_scalers; i++) {
9155 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9156 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9157 id = i;
9158 pipe_config->pch_pfit.enabled = true;
9159 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9160 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9161 break;
9162 }
9163 }
9164
9165 scaler_state->scaler_id = id;
9166 if (id >= 0) {
9167 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9168 } else {
9169 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9170 }
9171}
9172
9173static void
9174skylake_get_initial_plane_config(struct intel_crtc *crtc,
9175 struct intel_initial_plane_config *plane_config)
9176{
9177 struct drm_device *dev = crtc->base.dev;
9178 struct drm_i915_private *dev_priv = dev->dev_private;
9179 u32 val, base, stride_mult, tiling;
9180 int pipe = crtc->pipe;
9181 int fourcc, pixel_format;
9182 unsigned int aligned_height;
9183 struct drm_framebuffer *fb;
9184 struct intel_framebuffer *intel_fb;
9185
9186 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9187 if (!intel_fb) {
9188 DRM_DEBUG_KMS("failed to alloc fb\n");
9189 return;
9190 }
9191
9192 fb = &intel_fb->base;
9193
9194 val = I915_READ(PLANE_CTL(pipe, 0));
9195 if (!(val & PLANE_CTL_ENABLE))
9196 goto error;
9197
9198 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9199 fourcc = skl_format_to_fourcc(pixel_format,
9200 val & PLANE_CTL_ORDER_RGBX,
9201 val & PLANE_CTL_ALPHA_MASK);
9202 fb->pixel_format = fourcc;
9203 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9204
9205 tiling = val & PLANE_CTL_TILED_MASK;
9206 switch (tiling) {
9207 case PLANE_CTL_TILED_LINEAR:
9208 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9209 break;
9210 case PLANE_CTL_TILED_X:
9211 plane_config->tiling = I915_TILING_X;
9212 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9213 break;
9214 case PLANE_CTL_TILED_Y:
9215 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9216 break;
9217 case PLANE_CTL_TILED_YF:
9218 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9219 break;
9220 default:
9221 MISSING_CASE(tiling);
9222 goto error;
9223 }
9224
9225 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9226 plane_config->base = base;
9227
9228 (void)I915_READ(PLANE_OFFSET(pipe, 0));
9229
9230 val = I915_READ(PLANE_SIZE(pipe, 0));
9231 fb->height = ((val >> 16) & 0xfff) + 1;
9232 fb->width = ((val >> 0) & 0x1fff) + 1;
9233
9234 val = I915_READ(PLANE_STRIDE(pipe, 0));
9235 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9236 fb->pixel_format);
9237 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9238
9239 aligned_height = intel_fb_align_height(dev, fb->height,
9240 fb->pixel_format,
9241 fb->modifier[0]);
9242
9243 plane_config->size = fb->pitches[0] * aligned_height;
9244
9245 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9246 pipe_name(pipe), fb->width, fb->height,
9247 fb->bits_per_pixel, base, fb->pitches[0],
9248 plane_config->size);
9249
9250 plane_config->fb = intel_fb;
9251 return;
9252
9253error:
9254 kfree(fb);
9255}
9256
9257static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9258 struct intel_crtc_state *pipe_config)
9259{
9260 struct drm_device *dev = crtc->base.dev;
9261 struct drm_i915_private *dev_priv = dev->dev_private;
9262 uint32_t tmp;
9263
9264 tmp = I915_READ(PF_CTL(crtc->pipe));
9265
9266 if (tmp & PF_ENABLE) {
9267 pipe_config->pch_pfit.enabled = true;
9268 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9269 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9270
9271 /* We currently do not free assignements of panel fitters on
9272 * ivb/hsw (since we don't use the higher upscaling modes which
9273 * differentiates them) so just WARN about this case for now. */
9274 if (IS_GEN7(dev)) {
9275 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9276 PF_PIPE_SEL_IVB(crtc->pipe));
9277 }
9278 }
9279}
9280
9281static void
9282ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9283 struct intel_initial_plane_config *plane_config)
9284{
9285 struct drm_device *dev = crtc->base.dev;
9286 struct drm_i915_private *dev_priv = dev->dev_private;
9287 u32 val, base;
9288 int pipe = crtc->pipe;
9289 int fourcc, pixel_format;
9290 unsigned int aligned_height;
9291 struct drm_framebuffer *fb;
9292 struct intel_framebuffer *intel_fb;
9293
9294 val = I915_READ(DSPCNTR(pipe));
9295 if (!(val & DISPLAY_PLANE_ENABLE))
9296 return;
9297
9298 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9299 if (!intel_fb) {
9300 DRM_DEBUG_KMS("failed to alloc fb\n");
9301 return;
9302 }
9303
9304 fb = &intel_fb->base;
9305
9306 if (INTEL_INFO(dev)->gen >= 4) {
9307 if (val & DISPPLANE_TILED) {
9308 plane_config->tiling = I915_TILING_X;
9309 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9310 }
9311 }
9312
9313 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9314 fourcc = i9xx_format_to_fourcc(pixel_format);
9315 fb->pixel_format = fourcc;
9316 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9317
9318 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9319 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9320 (void)I915_READ(DSPOFFSET(pipe));
9321 } else {
9322 if (plane_config->tiling)
9323 (void)I915_READ(DSPTILEOFF(pipe));
9324 else
9325 (void)I915_READ(DSPLINOFF(pipe));
9326 }
9327 plane_config->base = base;
9328
9329 val = I915_READ(PIPESRC(pipe));
9330 fb->width = ((val >> 16) & 0xfff) + 1;
9331 fb->height = ((val >> 0) & 0xfff) + 1;
9332
9333 val = I915_READ(DSPSTRIDE(pipe));
9334 fb->pitches[0] = val & 0xffffffc0;
9335
9336 aligned_height = intel_fb_align_height(dev, fb->height,
9337 fb->pixel_format,
9338 fb->modifier[0]);
9339
9340 plane_config->size = fb->pitches[0] * aligned_height;
9341
9342 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9343 pipe_name(pipe), fb->width, fb->height,
9344 fb->bits_per_pixel, base, fb->pitches[0],
9345 plane_config->size);
9346
9347 plane_config->fb = intel_fb;
9348}
9349
9350static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9351 struct intel_crtc_state *pipe_config)
9352{
9353 struct drm_device *dev = crtc->base.dev;
9354 struct drm_i915_private *dev_priv = dev->dev_private;
9355 uint32_t tmp;
9356
9357 if (!intel_display_power_is_enabled(dev_priv,
9358 POWER_DOMAIN_PIPE(crtc->pipe)))
9359 return false;
9360
9361 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9362 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9363
9364 tmp = I915_READ(PIPECONF(crtc->pipe));
9365 if (!(tmp & PIPECONF_ENABLE))
9366 return false;
9367
9368 switch (tmp & PIPECONF_BPC_MASK) {
9369 case PIPECONF_6BPC:
9370 pipe_config->pipe_bpp = 18;
9371 break;
9372 case PIPECONF_8BPC:
9373 pipe_config->pipe_bpp = 24;
9374 break;
9375 case PIPECONF_10BPC:
9376 pipe_config->pipe_bpp = 30;
9377 break;
9378 case PIPECONF_12BPC:
9379 pipe_config->pipe_bpp = 36;
9380 break;
9381 default:
9382 break;
9383 }
9384
9385 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9386 pipe_config->limited_color_range = true;
9387
9388 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9389 struct intel_shared_dpll *pll;
9390
9391 pipe_config->has_pch_encoder = true;
9392
9393 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9394 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9395 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9396
9397 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9398
9399 if (HAS_PCH_IBX(dev_priv->dev)) {
9400 pipe_config->shared_dpll =
9401 (enum intel_dpll_id) crtc->pipe;
9402 } else {
9403 tmp = I915_READ(PCH_DPLL_SEL);
9404 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9405 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9406 else
9407 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9408 }
9409
9410 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9411
9412 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9413 &pipe_config->dpll_hw_state));
9414
9415 tmp = pipe_config->dpll_hw_state.dpll;
9416 pipe_config->pixel_multiplier =
9417 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9418 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9419
9420 ironlake_pch_clock_get(crtc, pipe_config);
9421 } else {
9422 pipe_config->pixel_multiplier = 1;
9423 }
9424
9425 intel_get_pipe_timings(crtc, pipe_config);
9426
9427 ironlake_get_pfit_config(crtc, pipe_config);
9428
9429 return true;
9430}
9431
9432static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9433{
9434 struct drm_device *dev = dev_priv->dev;
9435 struct intel_crtc *crtc;
9436
9437 for_each_intel_crtc(dev, crtc)
9438 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9439 pipe_name(crtc->pipe));
9440
9441 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9442 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9443 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9444 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9445 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9446 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9447 "CPU PWM1 enabled\n");
9448 if (IS_HASWELL(dev))
9449 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9450 "CPU PWM2 enabled\n");
9451 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9452 "PCH PWM1 enabled\n");
9453 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9454 "Utility pin enabled\n");
9455 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9456
9457 /*
9458 * In theory we can still leave IRQs enabled, as long as only the HPD
9459 * interrupts remain enabled. We used to check for that, but since it's
9460 * gen-specific and since we only disable LCPLL after we fully disable
9461 * the interrupts, the check below should be enough.
9462 */
9463 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9464}
9465
9466static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9467{
9468 struct drm_device *dev = dev_priv->dev;
9469
9470 if (IS_HASWELL(dev))
9471 return I915_READ(D_COMP_HSW);
9472 else
9473 return I915_READ(D_COMP_BDW);
9474}
9475
9476static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9477{
9478 struct drm_device *dev = dev_priv->dev;
9479
9480 if (IS_HASWELL(dev)) {
9481 mutex_lock(&dev_priv->rps.hw_lock);
9482 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9483 val))
9484 DRM_ERROR("Failed to write to D_COMP\n");
9485 mutex_unlock(&dev_priv->rps.hw_lock);
9486 } else {
9487 I915_WRITE(D_COMP_BDW, val);
9488 POSTING_READ(D_COMP_BDW);
9489 }
9490}
9491
9492/*
9493 * This function implements pieces of two sequences from BSpec:
9494 * - Sequence for display software to disable LCPLL
9495 * - Sequence for display software to allow package C8+
9496 * The steps implemented here are just the steps that actually touch the LCPLL
9497 * register. Callers should take care of disabling all the display engine
9498 * functions, doing the mode unset, fixing interrupts, etc.
9499 */
9500static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9501 bool switch_to_fclk, bool allow_power_down)
9502{
9503 uint32_t val;
9504
9505 assert_can_disable_lcpll(dev_priv);
9506
9507 val = I915_READ(LCPLL_CTL);
9508
9509 if (switch_to_fclk) {
9510 val |= LCPLL_CD_SOURCE_FCLK;
9511 I915_WRITE(LCPLL_CTL, val);
9512
9513 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9514 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9515 DRM_ERROR("Switching to FCLK failed\n");
9516
9517 val = I915_READ(LCPLL_CTL);
9518 }
9519
9520 val |= LCPLL_PLL_DISABLE;
9521 I915_WRITE(LCPLL_CTL, val);
9522 POSTING_READ(LCPLL_CTL);
9523
9524 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9525 DRM_ERROR("LCPLL still locked\n");
9526
9527 val = hsw_read_dcomp(dev_priv);
9528 val |= D_COMP_COMP_DISABLE;
9529 hsw_write_dcomp(dev_priv, val);
9530 ndelay(100);
9531
9532 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9533 1))
9534 DRM_ERROR("D_COMP RCOMP still in progress\n");
9535
9536 if (allow_power_down) {
9537 val = I915_READ(LCPLL_CTL);
9538 val |= LCPLL_POWER_DOWN_ALLOW;
9539 I915_WRITE(LCPLL_CTL, val);
9540 POSTING_READ(LCPLL_CTL);
9541 }
9542}
9543
9544/*
9545 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9546 * source.
9547 */
9548static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9549{
9550 uint32_t val;
9551
9552 val = I915_READ(LCPLL_CTL);
9553
9554 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9555 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9556 return;
9557
9558 /*
9559 * Make sure we're not on PC8 state before disabling PC8, otherwise
9560 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9561 */
9562 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9563
9564 if (val & LCPLL_POWER_DOWN_ALLOW) {
9565 val &= ~LCPLL_POWER_DOWN_ALLOW;
9566 I915_WRITE(LCPLL_CTL, val);
9567 POSTING_READ(LCPLL_CTL);
9568 }
9569
9570 val = hsw_read_dcomp(dev_priv);
9571 val |= D_COMP_COMP_FORCE;
9572 val &= ~D_COMP_COMP_DISABLE;
9573 hsw_write_dcomp(dev_priv, val);
9574
9575 val = I915_READ(LCPLL_CTL);
9576 val &= ~LCPLL_PLL_DISABLE;
9577 I915_WRITE(LCPLL_CTL, val);
9578
9579 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9580 DRM_ERROR("LCPLL not locked yet\n");
9581
9582 if (val & LCPLL_CD_SOURCE_FCLK) {
9583 val = I915_READ(LCPLL_CTL);
9584 val &= ~LCPLL_CD_SOURCE_FCLK;
9585 I915_WRITE(LCPLL_CTL, val);
9586
9587 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9588 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9589 DRM_ERROR("Switching back to LCPLL failed\n");
9590 }
9591
9592 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9593 intel_update_cdclk(dev_priv->dev);
9594}
9595
9596/*
9597 * Package states C8 and deeper are really deep PC states that can only be
9598 * reached when all the devices on the system allow it, so even if the graphics
9599 * device allows PC8+, it doesn't mean the system will actually get to these
9600 * states. Our driver only allows PC8+ when going into runtime PM.
9601 *
9602 * The requirements for PC8+ are that all the outputs are disabled, the power
9603 * well is disabled and most interrupts are disabled, and these are also
9604 * requirements for runtime PM. When these conditions are met, we manually do
9605 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9606 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9607 * hang the machine.
9608 *
9609 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9610 * the state of some registers, so when we come back from PC8+ we need to
9611 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9612 * need to take care of the registers kept by RC6. Notice that this happens even
9613 * if we don't put the device in PCI D3 state (which is what currently happens
9614 * because of the runtime PM support).
9615 *
9616 * For more, read "Display Sequences for Package C8" on the hardware
9617 * documentation.
9618 */
9619void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9620{
9621 struct drm_device *dev = dev_priv->dev;
9622 uint32_t val;
9623
9624 DRM_DEBUG_KMS("Enabling package C8+\n");
9625
9626 if (HAS_PCH_LPT_LP(dev)) {
9627 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9628 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9629 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9630 }
9631
9632 lpt_disable_clkout_dp(dev);
9633 hsw_disable_lcpll(dev_priv, true, true);
9634}
9635
9636void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9637{
9638 struct drm_device *dev = dev_priv->dev;
9639 uint32_t val;
9640
9641 DRM_DEBUG_KMS("Disabling package C8+\n");
9642
9643 hsw_restore_lcpll(dev_priv);
9644 lpt_init_pch_refclk(dev);
9645
9646 if (HAS_PCH_LPT_LP(dev)) {
9647 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9648 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9649 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9650 }
9651
9652 intel_prepare_ddi(dev);
9653}
9654
9655static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9656{
9657 struct drm_device *dev = old_state->dev;
9658 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9659
9660 broxton_set_cdclk(dev, req_cdclk);
9661}
9662
9663/* compute the max rate for new configuration */
9664static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9665{
9666 struct intel_crtc *intel_crtc;
9667 struct intel_crtc_state *crtc_state;
9668 int max_pixel_rate = 0;
9669
9670 for_each_intel_crtc(state->dev, intel_crtc) {
9671 int pixel_rate;
9672
9673 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9674 if (IS_ERR(crtc_state))
9675 return PTR_ERR(crtc_state);
9676
9677 if (!crtc_state->base.enable)
9678 continue;
9679
9680 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9681
9682 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9683 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9684 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9685
9686 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9687 }
9688
9689 return max_pixel_rate;
9690}
9691
9692static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9693{
9694 struct drm_i915_private *dev_priv = dev->dev_private;
9695 uint32_t val, data;
9696 int ret;
9697
9698 if (WARN((I915_READ(LCPLL_CTL) &
9699 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9700 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9701 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9702 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9703 "trying to change cdclk frequency with cdclk not enabled\n"))
9704 return;
9705
9706 mutex_lock(&dev_priv->rps.hw_lock);
9707 ret = sandybridge_pcode_write(dev_priv,
9708 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9709 mutex_unlock(&dev_priv->rps.hw_lock);
9710 if (ret) {
9711 DRM_ERROR("failed to inform pcode about cdclk change\n");
9712 return;
9713 }
9714
9715 val = I915_READ(LCPLL_CTL);
9716 val |= LCPLL_CD_SOURCE_FCLK;
9717 I915_WRITE(LCPLL_CTL, val);
9718
9719 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9720 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9721 DRM_ERROR("Switching to FCLK failed\n");
9722
9723 val = I915_READ(LCPLL_CTL);
9724 val &= ~LCPLL_CLK_FREQ_MASK;
9725
9726 switch (cdclk) {
9727 case 450000:
9728 val |= LCPLL_CLK_FREQ_450;
9729 data = 0;
9730 break;
9731 case 540000:
9732 val |= LCPLL_CLK_FREQ_54O_BDW;
9733 data = 1;
9734 break;
9735 case 337500:
9736 val |= LCPLL_CLK_FREQ_337_5_BDW;
9737 data = 2;
9738 break;
9739 case 675000:
9740 val |= LCPLL_CLK_FREQ_675_BDW;
9741 data = 3;
9742 break;
9743 default:
9744 WARN(1, "invalid cdclk frequency\n");
9745 return;
9746 }
9747
9748 I915_WRITE(LCPLL_CTL, val);
9749
9750 val = I915_READ(LCPLL_CTL);
9751 val &= ~LCPLL_CD_SOURCE_FCLK;
9752 I915_WRITE(LCPLL_CTL, val);
9753
9754 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9755 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9756 DRM_ERROR("Switching back to LCPLL failed\n");
9757
9758 mutex_lock(&dev_priv->rps.hw_lock);
9759 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9760 mutex_unlock(&dev_priv->rps.hw_lock);
9761
9762 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9763
9764 intel_update_cdclk(dev);
9765
9766 WARN(cdclk != dev_priv->cdclk_freq,
9767 "cdclk requested %d kHz but got %d kHz\n",
9768 cdclk, dev_priv->cdclk_freq);
9769}
9770
9771static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9772{
9773 struct drm_i915_private *dev_priv = to_i915(state->dev);
9774 int max_pixclk = ilk_max_pixel_rate(state);
9775 int cdclk;
9776
9777 /*
9778 * FIXME should also account for plane ratio
9779 * once 64bpp pixel formats are supported.
9780 */
9781 if (max_pixclk > 540000)
9782 cdclk = 675000;
9783 else if (max_pixclk > 450000)
9784 cdclk = 540000;
9785 else if (max_pixclk > 337500)
9786 cdclk = 450000;
9787 else
9788 cdclk = 337500;
9789
9790 /*
9791 * FIXME move the cdclk caclulation to
9792 * compute_config() so we can fail gracegully.
9793 */
9794 if (cdclk > dev_priv->max_cdclk_freq) {
9795 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9796 cdclk, dev_priv->max_cdclk_freq);
9797 cdclk = dev_priv->max_cdclk_freq;
9798 }
9799
9800 to_intel_atomic_state(state)->cdclk = cdclk;
9801
9802 return 0;
9803}
9804
9805static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9806{
9807 struct drm_device *dev = old_state->dev;
9808 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9809
9810 broadwell_set_cdclk(dev, req_cdclk);
9811}
9812
9813static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9814 struct intel_crtc_state *crtc_state)
9815{
9816 if (!intel_ddi_pll_select(crtc, crtc_state))
9817 return -EINVAL;
9818
9819 crtc->lowfreq_avail = false;
9820
9821 return 0;
9822}
9823
9824static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9825 enum port port,
9826 struct intel_crtc_state *pipe_config)
9827{
9828 switch (port) {
9829 case PORT_A:
9830 pipe_config->ddi_pll_sel = SKL_DPLL0;
9831 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9832 break;
9833 case PORT_B:
9834 pipe_config->ddi_pll_sel = SKL_DPLL1;
9835 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9836 break;
9837 case PORT_C:
9838 pipe_config->ddi_pll_sel = SKL_DPLL2;
9839 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9840 break;
9841 default:
9842 DRM_ERROR("Incorrect port type\n");
9843 }
9844}
9845
9846static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9847 enum port port,
9848 struct intel_crtc_state *pipe_config)
9849{
9850 u32 temp, dpll_ctl1;
9851
9852 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9853 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9854
9855 switch (pipe_config->ddi_pll_sel) {
9856 case SKL_DPLL0:
9857 /*
9858 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9859 * of the shared DPLL framework and thus needs to be read out
9860 * separately
9861 */
9862 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9863 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9864 break;
9865 case SKL_DPLL1:
9866 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9867 break;
9868 case SKL_DPLL2:
9869 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9870 break;
9871 case SKL_DPLL3:
9872 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9873 break;
9874 }
9875}
9876
9877static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9878 enum port port,
9879 struct intel_crtc_state *pipe_config)
9880{
9881 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9882
9883 switch (pipe_config->ddi_pll_sel) {
9884 case PORT_CLK_SEL_WRPLL1:
9885 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9886 break;
9887 case PORT_CLK_SEL_WRPLL2:
9888 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9889 break;
9890 case PORT_CLK_SEL_SPLL:
9891 pipe_config->shared_dpll = DPLL_ID_SPLL;
9892 }
9893}
9894
9895static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9896 struct intel_crtc_state *pipe_config)
9897{
9898 struct drm_device *dev = crtc->base.dev;
9899 struct drm_i915_private *dev_priv = dev->dev_private;
9900 struct intel_shared_dpll *pll;
9901 enum port port;
9902 uint32_t tmp;
9903
9904 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9905
9906 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9907
9908 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9909 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9910 else if (IS_BROXTON(dev))
9911 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9912 else
9913 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9914
9915 if (pipe_config->shared_dpll >= 0) {
9916 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9917
9918 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9919 &pipe_config->dpll_hw_state));
9920 }
9921
9922 /*
9923 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9924 * DDI E. So just check whether this pipe is wired to DDI E and whether
9925 * the PCH transcoder is on.
9926 */
9927 if (INTEL_INFO(dev)->gen < 9 &&
9928 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9929 pipe_config->has_pch_encoder = true;
9930
9931 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9932 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9933 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9934
9935 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9936 }
9937}
9938
9939static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9940 struct intel_crtc_state *pipe_config)
9941{
9942 struct drm_device *dev = crtc->base.dev;
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944 enum intel_display_power_domain pfit_domain;
9945 uint32_t tmp;
9946
9947 if (!intel_display_power_is_enabled(dev_priv,
9948 POWER_DOMAIN_PIPE(crtc->pipe)))
9949 return false;
9950
9951 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9952 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9953
9954 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9955 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9956 enum i915_pipe trans_edp_pipe;
9957 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9958 default:
9959 WARN(1, "unknown pipe linked to edp transcoder\n");
9960 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9961 case TRANS_DDI_EDP_INPUT_A_ON:
9962 trans_edp_pipe = PIPE_A;
9963 break;
9964 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9965 trans_edp_pipe = PIPE_B;
9966 break;
9967 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9968 trans_edp_pipe = PIPE_C;
9969 break;
9970 }
9971
9972 if (trans_edp_pipe == crtc->pipe)
9973 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9974 }
9975
9976 if (!intel_display_power_is_enabled(dev_priv,
9977 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9978 return false;
9979
9980 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9981 if (!(tmp & PIPECONF_ENABLE))
9982 return false;
9983
9984 haswell_get_ddi_port_state(crtc, pipe_config);
9985
9986 intel_get_pipe_timings(crtc, pipe_config);
9987
9988 if (INTEL_INFO(dev)->gen >= 9) {
9989 skl_init_scalers(dev, crtc, pipe_config);
9990 }
9991
9992 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9993
9994 if (INTEL_INFO(dev)->gen >= 9) {
9995 pipe_config->scaler_state.scaler_id = -1;
9996 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9997 }
9998
9999 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10000 if (INTEL_INFO(dev)->gen >= 9)
10001 skylake_get_pfit_config(crtc, pipe_config);
10002 else
10003 ironlake_get_pfit_config(crtc, pipe_config);
10004 }
10005
10006 if (IS_HASWELL(dev))
10007 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10008 (I915_READ(IPS_CTL) & IPS_ENABLE);
10009
10010 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10011 pipe_config->pixel_multiplier =
10012 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10013 } else {
10014 pipe_config->pixel_multiplier = 1;
10015 }
10016
10017 return true;
10018}
10019
10020static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10021{
10022 struct drm_device *dev = crtc->dev;
10023 struct drm_i915_private *dev_priv = dev->dev_private;
10024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10025 uint32_t cntl = 0, size = 0;
10026
10027 if (on) {
10028 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10029 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
10030 unsigned int stride = roundup_pow_of_two(width) * 4;
10031
10032 switch (stride) {
10033 default:
10034 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10035 width, stride);
10036 stride = 256;
10037 /* fallthrough */
10038 case 256:
10039 case 512:
10040 case 1024:
10041 case 2048:
10042 break;
10043 }
10044
10045 cntl |= CURSOR_ENABLE |
10046 CURSOR_GAMMA_ENABLE |
10047 CURSOR_FORMAT_ARGB |
10048 CURSOR_STRIDE(stride);
10049
10050 size = (height << 12) | width;
10051 }
10052
10053 if (intel_crtc->cursor_cntl != 0 &&
10054 (intel_crtc->cursor_base != base ||
10055 intel_crtc->cursor_size != size ||
10056 intel_crtc->cursor_cntl != cntl)) {
10057 /* On these chipsets we can only modify the base/size/stride
10058 * whilst the cursor is disabled.
10059 */
10060 I915_WRITE(CURCNTR(PIPE_A), 0);
10061 POSTING_READ(CURCNTR(PIPE_A));
10062 intel_crtc->cursor_cntl = 0;
10063 }
10064
10065 if (intel_crtc->cursor_base != base) {
10066 I915_WRITE(CURBASE(PIPE_A), base);
10067 intel_crtc->cursor_base = base;
10068 }
10069
10070 if (intel_crtc->cursor_size != size) {
10071 I915_WRITE(CURSIZE, size);
10072 intel_crtc->cursor_size = size;
10073 }
10074
10075 if (intel_crtc->cursor_cntl != cntl) {
10076 I915_WRITE(CURCNTR(PIPE_A), cntl);
10077 POSTING_READ(CURCNTR(PIPE_A));
10078 intel_crtc->cursor_cntl = cntl;
10079 }
10080}
10081
10082static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10083{
10084 struct drm_device *dev = crtc->dev;
10085 struct drm_i915_private *dev_priv = dev->dev_private;
10086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10087 int pipe = intel_crtc->pipe;
10088 uint32_t cntl = 0;
10089
10090 if (on) {
10091 cntl = MCURSOR_GAMMA_ENABLE;
10092 switch (intel_crtc->base.cursor->state->crtc_w) {
10093 case 64:
10094 cntl |= CURSOR_MODE_64_ARGB_AX;
10095 break;
10096 case 128:
10097 cntl |= CURSOR_MODE_128_ARGB_AX;
10098 break;
10099 case 256:
10100 cntl |= CURSOR_MODE_256_ARGB_AX;
10101 break;
10102 default:
10103 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10104 return;
10105 }
10106 cntl |= pipe << 28; /* Connect to correct pipe */
10107
10108 if (HAS_DDI(dev))
10109 cntl |= CURSOR_PIPE_CSC_ENABLE;
10110 }
10111
10112 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10113 cntl |= CURSOR_ROTATE_180;
10114
10115 if (intel_crtc->cursor_cntl != cntl) {
10116 I915_WRITE(CURCNTR(pipe), cntl);
10117 POSTING_READ(CURCNTR(pipe));
10118 intel_crtc->cursor_cntl = cntl;
10119 }
10120
10121 /* and commit changes on next vblank */
10122 I915_WRITE(CURBASE(pipe), base);
10123 POSTING_READ(CURBASE(pipe));
10124
10125 intel_crtc->cursor_base = base;
10126}
10127
10128/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10129static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10130 bool on)
10131{
10132 struct drm_device *dev = crtc->dev;
10133 struct drm_i915_private *dev_priv = dev->dev_private;
10134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10135 int pipe = intel_crtc->pipe;
10136 struct drm_plane_state *cursor_state = crtc->cursor->state;
10137 int x = cursor_state->crtc_x;
10138 int y = cursor_state->crtc_y;
10139 u32 base = 0, pos = 0;
10140
10141 base = intel_crtc->cursor_addr;
10142
10143 if (x >= intel_crtc->config->pipe_src_w)
10144 on = false;
10145
10146 if (y >= intel_crtc->config->pipe_src_h)
10147 on = false;
10148
10149 if (x < 0) {
10150 if (x + cursor_state->crtc_w <= 0)
10151 on = false;
10152
10153 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10154 x = -x;
10155 }
10156 pos |= x << CURSOR_X_SHIFT;
10157
10158 if (y < 0) {
10159 if (y + cursor_state->crtc_h <= 0)
10160 on = false;
10161
10162 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10163 y = -y;
10164 }
10165 pos |= y << CURSOR_Y_SHIFT;
10166
10167 I915_WRITE(CURPOS(pipe), pos);
10168
10169 /* ILK+ do this automagically */
10170 if (HAS_GMCH_DISPLAY(dev) &&
10171 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10172 base += (cursor_state->crtc_h *
10173 cursor_state->crtc_w - 1) * 4;
10174 }
10175
10176 if (IS_845G(dev) || IS_I865G(dev))
10177 i845_update_cursor(crtc, base, on);
10178 else
10179 i9xx_update_cursor(crtc, base, on);
10180}
10181
10182static bool cursor_size_ok(struct drm_device *dev,
10183 uint32_t width, uint32_t height)
10184{
10185 if (width == 0 || height == 0)
10186 return false;
10187
10188 /*
10189 * 845g/865g are special in that they are only limited by
10190 * the width of their cursors, the height is arbitrary up to
10191 * the precision of the register. Everything else requires
10192 * square cursors, limited to a few power-of-two sizes.
10193 */
10194 if (IS_845G(dev) || IS_I865G(dev)) {
10195 if ((width & 63) != 0)
10196 return false;
10197
10198 if (width > (IS_845G(dev) ? 64 : 512))
10199 return false;
10200
10201 if (height > 1023)
10202 return false;
10203 } else {
10204 switch (width | height) {
10205 case 256:
10206 case 128:
10207 if (IS_GEN2(dev))
10208 return false;
10209 case 64:
10210 break;
10211 default:
10212 return false;
10213 }
10214 }
10215
10216 return true;
10217}
10218
10219static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10220 u16 *blue, uint32_t start, uint32_t size)
10221{
10222 int end = (start + size > 256) ? 256 : start + size, i;
10223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10224
10225 for (i = start; i < end; i++) {
10226 intel_crtc->lut_r[i] = red[i] >> 8;
10227 intel_crtc->lut_g[i] = green[i] >> 8;
10228 intel_crtc->lut_b[i] = blue[i] >> 8;
10229 }
10230
10231 intel_crtc_load_lut(crtc);
10232}
10233
10234/* VESA 640x480x72Hz mode to set on the pipe */
10235static struct drm_display_mode load_detect_mode = {
10236 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10237 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10238};
10239
10240struct drm_framebuffer *
10241__intel_framebuffer_create(struct drm_device *dev,
10242 struct drm_mode_fb_cmd2 *mode_cmd,
10243 struct drm_i915_gem_object *obj)
10244{
10245 struct intel_framebuffer *intel_fb;
10246 int ret;
10247
10248 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10249 if (!intel_fb) {
10250 drm_gem_object_unreference(&obj->base);
10251 return ERR_PTR(-ENOMEM);
10252 }
10253
10254 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10255 if (ret)
10256 goto err;
10257
10258 return &intel_fb->base;
10259err:
10260 drm_gem_object_unreference(&obj->base);
10261 kfree(intel_fb);
10262
10263 return ERR_PTR(ret);
10264}
10265
10266static struct drm_framebuffer *
10267intel_framebuffer_create(struct drm_device *dev,
10268 struct drm_mode_fb_cmd2 *mode_cmd,
10269 struct drm_i915_gem_object *obj)
10270{
10271 struct drm_framebuffer *fb;
10272 int ret;
10273
10274 ret = i915_mutex_lock_interruptible(dev);
10275 if (ret)
10276 return ERR_PTR(ret);
10277 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10278 mutex_unlock(&dev->struct_mutex);
10279
10280 return fb;
10281}
10282
10283static u32
10284intel_framebuffer_pitch_for_width(int width, int bpp)
10285{
10286 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10287#ifdef __NetBSD__ /* XXX ALIGN means something else. */
10288 return round_up(pitch, 64);
10289#else
10290 return ALIGN(pitch, 64);
10291#endif
10292}
10293
10294static u32
10295intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10296{
10297 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10298 return PAGE_ALIGN(pitch * mode->vdisplay);
10299}
10300
10301static struct drm_framebuffer *
10302intel_framebuffer_create_for_mode(struct drm_device *dev,
10303 struct drm_display_mode *mode,
10304 int depth, int bpp)
10305{
10306 struct drm_i915_gem_object *obj;
10307 static const struct drm_mode_fb_cmd2 zero_mode_cmd;
10308 struct drm_mode_fb_cmd2 mode_cmd = zero_mode_cmd;
10309
10310 obj = i915_gem_alloc_object(dev,
10311 intel_framebuffer_size_for_mode(mode, bpp));
10312 if (obj == NULL)
10313 return ERR_PTR(-ENOMEM);
10314
10315 mode_cmd.width = mode->hdisplay;
10316 mode_cmd.height = mode->vdisplay;
10317 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10318 bpp);
10319 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10320
10321 return intel_framebuffer_create(dev, &mode_cmd, obj);
10322}
10323
10324static struct drm_framebuffer *
10325mode_fits_in_fbdev(struct drm_device *dev,
10326 struct drm_display_mode *mode)
10327{
10328#ifdef CONFIG_DRM_FBDEV_EMULATION
10329 struct drm_i915_private *dev_priv = dev->dev_private;
10330 struct drm_i915_gem_object *obj;
10331 struct drm_framebuffer *fb;
10332
10333 if (!dev_priv->fbdev)
10334 return NULL;
10335
10336 if (!dev_priv->fbdev->fb)
10337 return NULL;
10338
10339 obj = dev_priv->fbdev->fb->obj;
10340 BUG_ON(!obj);
10341
10342 fb = &dev_priv->fbdev->fb->base;
10343 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10344 fb->bits_per_pixel))
10345 return NULL;
10346
10347 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10348 return NULL;
10349
10350 return fb;
10351#else
10352 return NULL;
10353#endif
10354}
10355
10356static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10357 struct drm_crtc *crtc,
10358 struct drm_display_mode *mode,
10359 struct drm_framebuffer *fb,
10360 int x, int y)
10361{
10362 struct drm_plane_state *plane_state;
10363 int hdisplay, vdisplay;
10364 int ret;
10365
10366 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10367 if (IS_ERR(plane_state))
10368 return PTR_ERR(plane_state);
10369
10370 if (mode)
10371 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10372 else
10373 hdisplay = vdisplay = 0;
10374
10375 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10376 if (ret)
10377 return ret;
10378 drm_atomic_set_fb_for_plane(plane_state, fb);
10379 plane_state->crtc_x = 0;
10380 plane_state->crtc_y = 0;
10381 plane_state->crtc_w = hdisplay;
10382 plane_state->crtc_h = vdisplay;
10383 plane_state->src_x = x << 16;
10384 plane_state->src_y = y << 16;
10385 plane_state->src_w = hdisplay << 16;
10386 plane_state->src_h = vdisplay << 16;
10387
10388 return 0;
10389}
10390
10391bool intel_get_load_detect_pipe(struct drm_connector *connector,
10392 struct drm_display_mode *mode,
10393 struct intel_load_detect_pipe *old,
10394 struct drm_modeset_acquire_ctx *ctx)
10395{
10396 struct intel_crtc *intel_crtc;
10397 struct intel_encoder *intel_encoder =
10398 intel_attached_encoder(connector);
10399 struct drm_crtc *possible_crtc;
10400 struct drm_encoder *encoder = &intel_encoder->base;
10401 struct drm_crtc *crtc = NULL;
10402 struct drm_device *dev = encoder->dev;
10403 struct drm_framebuffer *fb;
10404 struct drm_mode_config *config = &dev->mode_config;
10405 struct drm_atomic_state *state = NULL;
10406 struct drm_connector_state *connector_state;
10407 struct intel_crtc_state *crtc_state;
10408 int ret, i = -1;
10409
10410 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10411 connector->base.id, connector->name,
10412 encoder->base.id, encoder->name);
10413
10414retry:
10415 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10416 if (ret)
10417 goto fail;
10418
10419 /*
10420 * Algorithm gets a little messy:
10421 *
10422 * - if the connector already has an assigned crtc, use it (but make
10423 * sure it's on first)
10424 *
10425 * - try to find the first unused crtc that can drive this connector,
10426 * and use that if we find one
10427 */
10428
10429 /* See if we already have a CRTC for this connector */
10430 if (encoder->crtc) {
10431 crtc = encoder->crtc;
10432
10433 ret = drm_modeset_lock(&crtc->mutex, ctx);
10434 if (ret)
10435 goto fail;
10436 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10437 if (ret)
10438 goto fail;
10439
10440 old->dpms_mode = connector->dpms;
10441 old->load_detect_temp = false;
10442
10443 /* Make sure the crtc and connector are running */
10444 if (connector->dpms != DRM_MODE_DPMS_ON)
10445 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10446
10447 return true;
10448 }
10449
10450 /* Find an unused one (if possible) */
10451 for_each_crtc(dev, possible_crtc) {
10452 i++;
10453 if (!(encoder->possible_crtcs & (1 << i)))
10454 continue;
10455 if (possible_crtc->state->enable)
10456 continue;
10457
10458 crtc = possible_crtc;
10459 break;
10460 }
10461
10462 /*
10463 * If we didn't find an unused CRTC, don't use any.
10464 */
10465 if (!crtc) {
10466 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10467 goto fail;
10468 }
10469
10470 ret = drm_modeset_lock(&crtc->mutex, ctx);
10471 if (ret)
10472 goto fail;
10473 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10474 if (ret)
10475 goto fail;
10476
10477 intel_crtc = to_intel_crtc(crtc);
10478 old->dpms_mode = connector->dpms;
10479 old->load_detect_temp = true;
10480 old->release_fb = NULL;
10481
10482 state = drm_atomic_state_alloc(dev);
10483 if (!state)
10484 return false;
10485
10486 state->acquire_ctx = ctx;
10487
10488 connector_state = drm_atomic_get_connector_state(state, connector);
10489 if (IS_ERR(connector_state)) {
10490 ret = PTR_ERR(connector_state);
10491 goto fail;
10492 }
10493
10494 connector_state->crtc = crtc;
10495 connector_state->best_encoder = &intel_encoder->base;
10496
10497 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10498 if (IS_ERR(crtc_state)) {
10499 ret = PTR_ERR(crtc_state);
10500 goto fail;
10501 }
10502
10503 crtc_state->base.active = crtc_state->base.enable = true;
10504
10505 if (!mode)
10506 mode = &load_detect_mode;
10507
10508 /* We need a framebuffer large enough to accommodate all accesses
10509 * that the plane may generate whilst we perform load detection.
10510 * We can not rely on the fbcon either being present (we get called
10511 * during its initialisation to detect all boot displays, or it may
10512 * not even exist) or that it is large enough to satisfy the
10513 * requested mode.
10514 */
10515 fb = mode_fits_in_fbdev(dev, mode);
10516 if (fb == NULL) {
10517 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10518 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10519 old->release_fb = fb;
10520 } else
10521 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10522 if (IS_ERR(fb)) {
10523 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10524 goto fail;
10525 }
10526
10527 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10528 if (ret)
10529 goto fail;
10530
10531 drm_mode_copy(&crtc_state->base.mode, mode);
10532
10533 if (drm_atomic_commit(state)) {
10534 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10535 if (old->release_fb)
10536 old->release_fb->funcs->destroy(old->release_fb);
10537 goto fail;
10538 }
10539 crtc->primary->crtc = crtc;
10540
10541 /* let the connector get through one full cycle before testing */
10542 intel_wait_for_vblank(dev, intel_crtc->pipe);
10543 return true;
10544
10545fail:
10546 drm_atomic_state_free(state);
10547 state = NULL;
10548
10549 if (ret == -EDEADLK) {
10550 drm_modeset_backoff(ctx);
10551 goto retry;
10552 }
10553
10554 return false;
10555}
10556
10557void intel_release_load_detect_pipe(struct drm_connector *connector,
10558 struct intel_load_detect_pipe *old,
10559 struct drm_modeset_acquire_ctx *ctx)
10560{
10561 struct drm_device *dev = connector->dev;
10562 struct intel_encoder *intel_encoder =
10563 intel_attached_encoder(connector);
10564 struct drm_encoder *encoder = &intel_encoder->base;
10565 struct drm_crtc *crtc = encoder->crtc;
10566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10567 struct drm_atomic_state *state;
10568 struct drm_connector_state *connector_state;
10569 struct intel_crtc_state *crtc_state;
10570 int ret;
10571
10572 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10573 connector->base.id, connector->name,
10574 encoder->base.id, encoder->name);
10575
10576 if (old->load_detect_temp) {
10577 state = drm_atomic_state_alloc(dev);
10578 if (!state)
10579 goto fail;
10580
10581 state->acquire_ctx = ctx;
10582
10583 connector_state = drm_atomic_get_connector_state(state, connector);
10584 if (IS_ERR(connector_state))
10585 goto fail;
10586
10587 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10588 if (IS_ERR(crtc_state))
10589 goto fail;
10590
10591 connector_state->best_encoder = NULL;
10592 connector_state->crtc = NULL;
10593
10594 crtc_state->base.enable = crtc_state->base.active = false;
10595
10596 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10597 0, 0);
10598 if (ret)
10599 goto fail;
10600
10601 ret = drm_atomic_commit(state);
10602 if (ret)
10603 goto fail;
10604
10605 if (old->release_fb) {
10606 drm_framebuffer_unregister_private(old->release_fb);
10607 drm_framebuffer_unreference(old->release_fb);
10608 }
10609
10610 return;
10611 }
10612
10613 /* Switch crtc and encoder back off if necessary */
10614 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10615 connector->funcs->dpms(connector, old->dpms_mode);
10616
10617 return;
10618fail:
10619 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10620 drm_atomic_state_free(state);
10621}
10622
10623static int i9xx_pll_refclk(struct drm_device *dev,
10624 const struct intel_crtc_state *pipe_config)
10625{
10626 struct drm_i915_private *dev_priv = dev->dev_private;
10627 u32 dpll = pipe_config->dpll_hw_state.dpll;
10628
10629 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10630 return dev_priv->vbt.lvds_ssc_freq;
10631 else if (HAS_PCH_SPLIT(dev))
10632 return 120000;
10633 else if (!IS_GEN2(dev))
10634 return 96000;
10635 else
10636 return 48000;
10637}
10638
10639/* Returns the clock of the currently programmed mode of the given pipe. */
10640static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10641 struct intel_crtc_state *pipe_config)
10642{
10643 struct drm_device *dev = crtc->base.dev;
10644 struct drm_i915_private *dev_priv = dev->dev_private;
10645 int pipe = pipe_config->cpu_transcoder;
10646 u32 dpll = pipe_config->dpll_hw_state.dpll;
10647 u32 fp;
10648 intel_clock_t clock;
10649 int port_clock;
10650 int refclk = i9xx_pll_refclk(dev, pipe_config);
10651
10652 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10653 fp = pipe_config->dpll_hw_state.fp0;
10654 else
10655 fp = pipe_config->dpll_hw_state.fp1;
10656
10657 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10658 if (IS_PINEVIEW(dev)) {
10659 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10660 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10661 } else {
10662 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10663 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10664 }
10665
10666 if (!IS_GEN2(dev)) {
10667 if (IS_PINEVIEW(dev))
10668 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10669 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10670 else
10671 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10672 DPLL_FPA01_P1_POST_DIV_SHIFT);
10673
10674 switch (dpll & DPLL_MODE_MASK) {
10675 case DPLLB_MODE_DAC_SERIAL:
10676 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10677 5 : 10;
10678 break;
10679 case DPLLB_MODE_LVDS:
10680 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10681 7 : 14;
10682 break;
10683 default:
10684 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10685 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10686 return;
10687 }
10688
10689 if (IS_PINEVIEW(dev))
10690 port_clock = pnv_calc_dpll_params(refclk, &clock);
10691 else
10692 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10693 } else {
10694 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10695 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10696
10697 if (is_lvds) {
10698 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10699 DPLL_FPA01_P1_POST_DIV_SHIFT);
10700
10701 if (lvds & LVDS_CLKB_POWER_UP)
10702 clock.p2 = 7;
10703 else
10704 clock.p2 = 14;
10705 } else {
10706 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10707 clock.p1 = 2;
10708 else {
10709 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10710 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10711 }
10712 if (dpll & PLL_P2_DIVIDE_BY_4)
10713 clock.p2 = 4;
10714 else
10715 clock.p2 = 2;
10716 }
10717
10718 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10719 }
10720
10721 /*
10722 * This value includes pixel_multiplier. We will use
10723 * port_clock to compute adjusted_mode.crtc_clock in the
10724 * encoder's get_config() function.
10725 */
10726 pipe_config->port_clock = port_clock;
10727}
10728
10729int intel_dotclock_calculate(int link_freq,
10730 const struct intel_link_m_n *m_n)
10731{
10732 /*
10733 * The calculation for the data clock is:
10734 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10735 * But we want to avoid losing precison if possible, so:
10736 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10737 *
10738 * and the link clock is simpler:
10739 * link_clock = (m * link_clock) / n
10740 */
10741
10742 if (!m_n->link_n)
10743 return 0;
10744
10745 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10746}
10747
10748static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10749 struct intel_crtc_state *pipe_config)
10750{
10751 struct drm_device *dev = crtc->base.dev;
10752
10753 /* read out port_clock from the DPLL */
10754 i9xx_crtc_clock_get(crtc, pipe_config);
10755
10756 /*
10757 * This value does not include pixel_multiplier.
10758 * We will check that port_clock and adjusted_mode.crtc_clock
10759 * agree once we know their relationship in the encoder's
10760 * get_config() function.
10761 */
10762 pipe_config->base.adjusted_mode.crtc_clock =
10763 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10764 &pipe_config->fdi_m_n);
10765}
10766
10767/** Returns the currently programmed mode of the given pipe. */
10768struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10769 struct drm_crtc *crtc)
10770{
10771 struct drm_i915_private *dev_priv = dev->dev_private;
10772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10773 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10774 struct drm_display_mode *mode;
10775 struct intel_crtc_state pipe_config;
10776 int htot = I915_READ(HTOTAL(cpu_transcoder));
10777 int hsync = I915_READ(HSYNC(cpu_transcoder));
10778 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10779 int vsync = I915_READ(VSYNC(cpu_transcoder));
10780 enum i915_pipe pipe = intel_crtc->pipe;
10781
10782 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10783 if (!mode)
10784 return NULL;
10785
10786 /*
10787 * Construct a pipe_config sufficient for getting the clock info
10788 * back out of crtc_clock_get.
10789 *
10790 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10791 * to use a real value here instead.
10792 */
10793 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10794 pipe_config.pixel_multiplier = 1;
10795 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10796 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10797 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10798 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10799
10800 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10801 mode->hdisplay = (htot & 0xffff) + 1;
10802 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10803 mode->hsync_start = (hsync & 0xffff) + 1;
10804 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10805 mode->vdisplay = (vtot & 0xffff) + 1;
10806 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10807 mode->vsync_start = (vsync & 0xffff) + 1;
10808 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10809
10810 drm_mode_set_name(mode);
10811
10812 return mode;
10813}
10814
10815void intel_mark_busy(struct drm_device *dev)
10816{
10817 struct drm_i915_private *dev_priv = dev->dev_private;
10818
10819 if (dev_priv->mm.busy)
10820 return;
10821
10822 intel_runtime_pm_get(dev_priv);
10823 i915_update_gfx_val(dev_priv);
10824 if (INTEL_INFO(dev)->gen >= 6)
10825 gen6_rps_busy(dev_priv);
10826 dev_priv->mm.busy = true;
10827}
10828
10829void intel_mark_idle(struct drm_device *dev)
10830{
10831 struct drm_i915_private *dev_priv = dev->dev_private;
10832
10833 if (!dev_priv->mm.busy)
10834 return;
10835
10836 dev_priv->mm.busy = false;
10837
10838 if (INTEL_INFO(dev)->gen >= 6)
10839 gen6_rps_idle(dev->dev_private);
10840
10841 intel_runtime_pm_put(dev_priv);
10842}
10843
10844static void intel_crtc_destroy(struct drm_crtc *crtc)
10845{
10846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10847 struct drm_device *dev = crtc->dev;
10848 struct intel_unpin_work *work;
10849
10850 spin_lock_irq(&dev->event_lock);
10851 work = intel_crtc->unpin_work;
10852 intel_crtc->unpin_work = NULL;
10853 spin_unlock_irq(&dev->event_lock);
10854
10855 if (work) {
10856 cancel_work_sync(&work->work);
10857 kfree(work);
10858 }
10859
10860 drm_crtc_cleanup(crtc);
10861
10862 kfree(intel_crtc);
10863}
10864
10865static void intel_unpin_work_fn(struct work_struct *__work)
10866{
10867 struct intel_unpin_work *work =
10868 container_of(__work, struct intel_unpin_work, work);
10869 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10870 struct drm_device *dev = crtc->base.dev;
10871 struct drm_plane *primary = crtc->base.primary;
10872
10873 mutex_lock(&dev->struct_mutex);
10874 intel_unpin_fb_obj(work->old_fb, primary->state);
10875 drm_gem_object_unreference(&work->pending_flip_obj->base);
10876
10877 if (work->flip_queued_req)
10878 i915_gem_request_assign(&work->flip_queued_req, NULL);
10879 mutex_unlock(&dev->struct_mutex);
10880
10881 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10882 drm_framebuffer_unreference(work->old_fb);
10883
10884 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10885 atomic_dec(&crtc->unpin_work_count);
10886
10887 kfree(work);
10888}
10889
10890static void do_intel_finish_page_flip(struct drm_device *dev,
10891 struct drm_crtc *crtc)
10892{
10893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10894 struct intel_unpin_work *work;
10895 unsigned long flags;
10896
10897 /* Ignore early vblank irqs */
10898 if (intel_crtc == NULL)
10899 return;
10900
10901 /*
10902 * This is called both by irq handlers and the reset code (to complete
10903 * lost pageflips) so needs the full irqsave spinlocks.
10904 */
10905 spin_lock_irqsave(&dev->event_lock, flags);
10906 work = intel_crtc->unpin_work;
10907
10908 /* Ensure we don't miss a work->pending update ... */
10909 smp_rmb();
10910
10911 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10912 spin_unlock_irqrestore(&dev->event_lock, flags);
10913 return;
10914 }
10915
10916 page_flip_completed(intel_crtc);
10917
10918 spin_unlock_irqrestore(&dev->event_lock, flags);
10919}
10920
10921void intel_finish_page_flip(struct drm_device *dev, int pipe)
10922{
10923 struct drm_i915_private *dev_priv = dev->dev_private;
10924 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10925
10926 do_intel_finish_page_flip(dev, crtc);
10927}
10928
10929void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10930{
10931 struct drm_i915_private *dev_priv = dev->dev_private;
10932 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10933
10934 do_intel_finish_page_flip(dev, crtc);
10935}
10936
10937/* Is 'a' after or equal to 'b'? */
10938static bool g4x_flip_count_after_eq(u32 a, u32 b)
10939{
10940 return !((a - b) & 0x80000000);
10941}
10942
10943static bool page_flip_finished(struct intel_crtc *crtc)
10944{
10945 struct drm_device *dev = crtc->base.dev;
10946 struct drm_i915_private *dev_priv = dev->dev_private;
10947
10948 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10949 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10950 return true;
10951
10952 /*
10953 * The relevant registers doen't exist on pre-ctg.
10954 * As the flip done interrupt doesn't trigger for mmio
10955 * flips on gmch platforms, a flip count check isn't
10956 * really needed there. But since ctg has the registers,
10957 * include it in the check anyway.
10958 */
10959 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10960 return true;
10961
10962 /*
10963 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10964 * used the same base address. In that case the mmio flip might
10965 * have completed, but the CS hasn't even executed the flip yet.
10966 *
10967 * A flip count check isn't enough as the CS might have updated
10968 * the base address just after start of vblank, but before we
10969 * managed to process the interrupt. This means we'd complete the
10970 * CS flip too soon.
10971 *
10972 * Combining both checks should get us a good enough result. It may
10973 * still happen that the CS flip has been executed, but has not
10974 * yet actually completed. But in case the base address is the same
10975 * anyway, we don't really care.
10976 */
10977 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10978 crtc->unpin_work->gtt_offset &&
10979 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10980 crtc->unpin_work->flip_count);
10981}
10982
10983void intel_prepare_page_flip(struct drm_device *dev, int plane)
10984{
10985 struct drm_i915_private *dev_priv = dev->dev_private;
10986 struct intel_crtc *intel_crtc =
10987 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10988 unsigned long flags;
10989
10990
10991 /*
10992 * This is called both by irq handlers and the reset code (to complete
10993 * lost pageflips) so needs the full irqsave spinlocks.
10994 *
10995 * NB: An MMIO update of the plane base pointer will also
10996 * generate a page-flip completion irq, i.e. every modeset
10997 * is also accompanied by a spurious intel_prepare_page_flip().
10998 */
10999 spin_lock_irqsave(&dev->event_lock, flags);
11000 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11001 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11002 spin_unlock_irqrestore(&dev->event_lock, flags);
11003}
11004
11005static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11006{
11007 /* Ensure that the work item is consistent when activating it ... */
11008 smp_wmb();
11009 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11010 /* and that it is marked active as soon as the irq could fire. */
11011 smp_wmb();
11012}
11013
11014static int intel_gen2_queue_flip(struct drm_device *dev,
11015 struct drm_crtc *crtc,
11016 struct drm_framebuffer *fb,
11017 struct drm_i915_gem_object *obj,
11018 struct drm_i915_gem_request *req,
11019 uint32_t flags)
11020{
11021 struct intel_engine_cs *ring = req->ring;
11022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11023 u32 flip_mask;
11024 int ret;
11025
11026 ret = intel_ring_begin(req, 6);
11027 if (ret)
11028 return ret;
11029
11030 /* Can't queue multiple flips, so wait for the previous
11031 * one to finish before executing the next.
11032 */
11033 if (intel_crtc->plane)
11034 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11035 else
11036 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11037 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11038 intel_ring_emit(ring, MI_NOOP);
11039 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11040 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11041 intel_ring_emit(ring, fb->pitches[0]);
11042 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11043 intel_ring_emit(ring, 0); /* aux display base address, unused */
11044
11045 intel_mark_page_flip_active(intel_crtc->unpin_work);
11046 return 0;
11047}
11048
11049static int intel_gen3_queue_flip(struct drm_device *dev,
11050 struct drm_crtc *crtc,
11051 struct drm_framebuffer *fb,
11052 struct drm_i915_gem_object *obj,
11053 struct drm_i915_gem_request *req,
11054 uint32_t flags)
11055{
11056 struct intel_engine_cs *ring = req->ring;
11057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11058 u32 flip_mask;
11059 int ret;
11060
11061 ret = intel_ring_begin(req, 6);
11062 if (ret)
11063 return ret;
11064
11065 if (intel_crtc->plane)
11066 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11067 else
11068 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11069 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11070 intel_ring_emit(ring, MI_NOOP);
11071 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11073 intel_ring_emit(ring, fb->pitches[0]);
11074 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11075 intel_ring_emit(ring, MI_NOOP);
11076
11077 intel_mark_page_flip_active(intel_crtc->unpin_work);
11078 return 0;
11079}
11080
11081static int intel_gen4_queue_flip(struct drm_device *dev,
11082 struct drm_crtc *crtc,
11083 struct drm_framebuffer *fb,
11084 struct drm_i915_gem_object *obj,
11085 struct drm_i915_gem_request *req,
11086 uint32_t flags)
11087{
11088 struct intel_engine_cs *ring = req->ring;
11089 struct drm_i915_private *dev_priv = dev->dev_private;
11090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11091 uint32_t pf, pipesrc;
11092 int ret;
11093
11094 ret = intel_ring_begin(req, 4);
11095 if (ret)
11096 return ret;
11097
11098 /* i965+ uses the linear or tiled offsets from the
11099 * Display Registers (which do not change across a page-flip)
11100 * so we need only reprogram the base address.
11101 */
11102 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11103 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11104 intel_ring_emit(ring, fb->pitches[0]);
11105 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11106 obj->tiling_mode);
11107
11108 /* XXX Enabling the panel-fitter across page-flip is so far
11109 * untested on non-native modes, so ignore it for now.
11110 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11111 */
11112 pf = 0;
11113 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11114 intel_ring_emit(ring, pf | pipesrc);
11115
11116 intel_mark_page_flip_active(intel_crtc->unpin_work);
11117 return 0;
11118}
11119
11120static int intel_gen6_queue_flip(struct drm_device *dev,
11121 struct drm_crtc *crtc,
11122 struct drm_framebuffer *fb,
11123 struct drm_i915_gem_object *obj,
11124 struct drm_i915_gem_request *req,
11125 uint32_t flags)
11126{
11127 struct intel_engine_cs *ring = req->ring;
11128 struct drm_i915_private *dev_priv = dev->dev_private;
11129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11130 uint32_t pf, pipesrc;
11131 int ret;
11132
11133 ret = intel_ring_begin(req, 4);
11134 if (ret)
11135 return ret;
11136
11137 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11139 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11140 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11141
11142 /* Contrary to the suggestions in the documentation,
11143 * "Enable Panel Fitter" does not seem to be required when page
11144 * flipping with a non-native mode, and worse causes a normal
11145 * modeset to fail.
11146 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11147 */
11148 pf = 0;
11149 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11150 intel_ring_emit(ring, pf | pipesrc);
11151
11152 intel_mark_page_flip_active(intel_crtc->unpin_work);
11153 return 0;
11154}
11155
11156static int intel_gen7_queue_flip(struct drm_device *dev,
11157 struct drm_crtc *crtc,
11158 struct drm_framebuffer *fb,
11159 struct drm_i915_gem_object *obj,
11160 struct drm_i915_gem_request *req,
11161 uint32_t flags)
11162{
11163 struct intel_engine_cs *ring = req->ring;
11164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11165 uint32_t plane_bit = 0;
11166 int len, ret;
11167
11168 switch (intel_crtc->plane) {
11169 case PLANE_A:
11170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11171 break;
11172 case PLANE_B:
11173 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11174 break;
11175 case PLANE_C:
11176 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11177 break;
11178 default:
11179 WARN_ONCE(1, "unknown plane in flip command\n");
11180 return -ENODEV;
11181 }
11182
11183 len = 4;
11184 if (ring->id == RCS) {
11185 len += 6;
11186 /*
11187 * On Gen 8, SRM is now taking an extra dword to accommodate
11188 * 48bits addresses, and we need a NOOP for the batch size to
11189 * stay even.
11190 */
11191 if (IS_GEN8(dev))
11192 len += 2;
11193 }
11194
11195 /*
11196 * BSpec MI_DISPLAY_FLIP for IVB:
11197 * "The full packet must be contained within the same cache line."
11198 *
11199 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11200 * cacheline, if we ever start emitting more commands before
11201 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11202 * then do the cacheline alignment, and finally emit the
11203 * MI_DISPLAY_FLIP.
11204 */
11205 ret = intel_ring_cacheline_align(req);
11206 if (ret)
11207 return ret;
11208
11209 ret = intel_ring_begin(req, len);
11210 if (ret)
11211 return ret;
11212
11213 /* Unmask the flip-done completion message. Note that the bspec says that
11214 * we should do this for both the BCS and RCS, and that we must not unmask
11215 * more than one flip event at any time (or ensure that one flip message
11216 * can be sent by waiting for flip-done prior to queueing new flips).
11217 * Experimentation says that BCS works despite DERRMR masking all
11218 * flip-done completion events and that unmasking all planes at once
11219 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11220 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11221 */
11222 if (ring->id == RCS) {
11223 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11224 intel_ring_emit(ring, DERRMR);
11225 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11226 DERRMR_PIPEB_PRI_FLIP_DONE |
11227 DERRMR_PIPEC_PRI_FLIP_DONE));
11228 if (IS_GEN8(dev))
11229 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11230 MI_SRM_LRM_GLOBAL_GTT);
11231 else
11232 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11233 MI_SRM_LRM_GLOBAL_GTT);
11234 intel_ring_emit(ring, DERRMR);
11235 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11236 if (IS_GEN8(dev)) {
11237 intel_ring_emit(ring, 0);
11238 intel_ring_emit(ring, MI_NOOP);
11239 }
11240 }
11241
11242 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11243 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11244 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11245 intel_ring_emit(ring, (MI_NOOP));
11246
11247 intel_mark_page_flip_active(intel_crtc->unpin_work);
11248 return 0;
11249}
11250
11251static bool use_mmio_flip(struct intel_engine_cs *ring,
11252 struct drm_i915_gem_object *obj)
11253{
11254 /*
11255 * This is not being used for older platforms, because
11256 * non-availability of flip done interrupt forces us to use
11257 * CS flips. Older platforms derive flip done using some clever
11258 * tricks involving the flip_pending status bits and vblank irqs.
11259 * So using MMIO flips there would disrupt this mechanism.
11260 */
11261
11262 if (ring == NULL)
11263 return true;
11264
11265 if (INTEL_INFO(ring->dev)->gen < 5)
11266 return false;
11267
11268 if (i915.use_mmio_flip < 0)
11269 return false;
11270 else if (i915.use_mmio_flip > 0)
11271 return true;
11272 else if (i915.enable_execlists)
11273 return true;
11274 else
11275 return ring != i915_gem_request_get_ring(obj->last_write_req);
11276}
11277
11278static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11279 struct intel_unpin_work *work)
11280{
11281 struct drm_device *dev = intel_crtc->base.dev;
11282 struct drm_i915_private *dev_priv = dev->dev_private;
11283 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11284 const enum i915_pipe pipe = intel_crtc->pipe;
11285 u32 ctl, stride;
11286
11287 ctl = I915_READ(PLANE_CTL(pipe, 0));
11288 ctl &= ~PLANE_CTL_TILED_MASK;
11289 switch (fb->modifier[0]) {
11290 case DRM_FORMAT_MOD_NONE:
11291 break;
11292 case I915_FORMAT_MOD_X_TILED:
11293 ctl |= PLANE_CTL_TILED_X;
11294 break;
11295 case I915_FORMAT_MOD_Y_TILED:
11296 ctl |= PLANE_CTL_TILED_Y;
11297 break;
11298 case I915_FORMAT_MOD_Yf_TILED:
11299 ctl |= PLANE_CTL_TILED_YF;
11300 break;
11301 default:
11302 MISSING_CASE(fb->modifier[0]);
11303 }
11304
11305 /*
11306 * The stride is either expressed as a multiple of 64 bytes chunks for
11307 * linear buffers or in number of tiles for tiled buffers.
11308 */
11309 stride = fb->pitches[0] /
11310 intel_fb_stride_alignment(dev, fb->modifier[0],
11311 fb->pixel_format);
11312
11313 /*
11314 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11315 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11316 */
11317 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11318 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11319
11320 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11321 POSTING_READ(PLANE_SURF(pipe, 0));
11322}
11323
11324static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11325 struct intel_unpin_work *work)
11326{
11327 struct drm_device *dev = intel_crtc->base.dev;
11328 struct drm_i915_private *dev_priv = dev->dev_private;
11329 struct intel_framebuffer *intel_fb =
11330 to_intel_framebuffer(intel_crtc->base.primary->fb);
11331 struct drm_i915_gem_object *obj = intel_fb->obj;
11332 u32 dspcntr;
11333 u32 reg;
11334
11335 reg = DSPCNTR(intel_crtc->plane);
11336 dspcntr = I915_READ(reg);
11337
11338 if (obj->tiling_mode != I915_TILING_NONE)
11339 dspcntr |= DISPPLANE_TILED;
11340 else
11341 dspcntr &= ~DISPPLANE_TILED;
11342
11343 I915_WRITE(reg, dspcntr);
11344
11345 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11346 POSTING_READ(DSPSURF(intel_crtc->plane));
11347}
11348
11349/*
11350 * XXX: This is the temporary way to update the plane registers until we get
11351 * around to using the usual plane update functions for MMIO flips
11352 */
11353static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11354{
11355 struct intel_crtc *crtc = mmio_flip->crtc;
11356 struct intel_unpin_work *work;
11357
11358 spin_lock_irq(&crtc->base.dev->event_lock);
11359 work = crtc->unpin_work;
11360 spin_unlock_irq(&crtc->base.dev->event_lock);
11361 if (work == NULL)
11362 return;
11363
11364 intel_mark_page_flip_active(work);
11365
11366 intel_pipe_update_start(crtc);
11367
11368 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11369 skl_do_mmio_flip(crtc, work);
11370 else
11371 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11372 ilk_do_mmio_flip(crtc, work);
11373
11374 intel_pipe_update_end(crtc);
11375}
11376
11377static void intel_mmio_flip_work_func(struct work_struct *work)
11378{
11379 struct intel_mmio_flip *mmio_flip =
11380 container_of(work, struct intel_mmio_flip, work);
11381
11382 if (mmio_flip->req) {
11383 WARN_ON(__i915_wait_request(mmio_flip->req,
11384 mmio_flip->crtc->reset_counter,
11385 false, NULL,
11386 &mmio_flip->i915->rps.mmioflips));
11387 i915_gem_request_unreference__unlocked(mmio_flip->req);
11388 }
11389
11390 intel_do_mmio_flip(mmio_flip);
11391 kfree(mmio_flip);
11392}
11393
11394static int intel_queue_mmio_flip(struct drm_device *dev,
11395 struct drm_crtc *crtc,
11396 struct drm_framebuffer *fb,
11397 struct drm_i915_gem_object *obj,
11398 struct intel_engine_cs *ring,
11399 uint32_t flags)
11400{
11401 struct intel_mmio_flip *mmio_flip;
11402
11403 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11404 if (mmio_flip == NULL)
11405 return -ENOMEM;
11406
11407 mmio_flip->i915 = to_i915(dev);
11408 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11409 mmio_flip->crtc = to_intel_crtc(crtc);
11410
11411 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11412 schedule_work(&mmio_flip->work);
11413
11414 return 0;
11415}
11416
11417static int intel_default_queue_flip(struct drm_device *dev,
11418 struct drm_crtc *crtc,
11419 struct drm_framebuffer *fb,
11420 struct drm_i915_gem_object *obj,
11421 struct drm_i915_gem_request *req,
11422 uint32_t flags)
11423{
11424 return -ENODEV;
11425}
11426
11427static bool __intel_pageflip_stall_check(struct drm_device *dev,
11428 struct drm_crtc *crtc)
11429{
11430 struct drm_i915_private *dev_priv = dev->dev_private;
11431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11432 struct intel_unpin_work *work = intel_crtc->unpin_work;
11433 u32 addr;
11434
11435 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11436 return true;
11437
11438 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11439 return false;
11440
11441 if (!work->enable_stall_check)
11442 return false;
11443
11444 if (work->flip_ready_vblank == 0) {
11445 if (work->flip_queued_req &&
11446 !i915_gem_request_completed(work->flip_queued_req, true))
11447 return false;
11448
11449 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11450 }
11451
11452 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11453 return false;
11454
11455 /* Potential stall - if we see that the flip has happened,
11456 * assume a missed interrupt. */
11457 if (INTEL_INFO(dev)->gen >= 4)
11458 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11459 else
11460 addr = I915_READ(DSPADDR(intel_crtc->plane));
11461
11462 /* There is a potential issue here with a false positive after a flip
11463 * to the same address. We could address this by checking for a
11464 * non-incrementing frame counter.
11465 */
11466 return addr == work->gtt_offset;
11467}
11468
11469void intel_check_page_flip(struct drm_device *dev, int pipe)
11470{
11471 struct drm_i915_private *dev_priv = dev->dev_private;
11472 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11474 struct intel_unpin_work *work;
11475
11476 WARN_ON(!in_interrupt());
11477
11478 if (crtc == NULL)
11479 return;
11480
11481 spin_lock(&dev->event_lock);
11482 work = intel_crtc->unpin_work;
11483 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11484 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11485 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11486 page_flip_completed(intel_crtc);
11487 work = NULL;
11488 }
11489 if (work != NULL &&
11490 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11491 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11492 spin_unlock(&dev->event_lock);
11493}
11494
11495static int intel_crtc_page_flip(struct drm_crtc *crtc,
11496 struct drm_framebuffer *fb,
11497 struct drm_pending_vblank_event *event,
11498 uint32_t page_flip_flags)
11499{
11500 struct drm_device *dev = crtc->dev;
11501 struct drm_i915_private *dev_priv = dev->dev_private;
11502 struct drm_framebuffer *old_fb = crtc->primary->fb;
11503 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11505 struct drm_plane *primary = crtc->primary;
11506 enum i915_pipe pipe = intel_crtc->pipe;
11507 struct intel_unpin_work *work;
11508 struct intel_engine_cs *ring;
11509 bool mmio_flip;
11510 struct drm_i915_gem_request *request = NULL;
11511 int ret;
11512
11513 /*
11514 * drm_mode_page_flip_ioctl() should already catch this, but double
11515 * check to be safe. In the future we may enable pageflipping from
11516 * a disabled primary plane.
11517 */
11518 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11519 return -EBUSY;
11520
11521 /* Can't change pixel format via MI display flips. */
11522 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11523 return -EINVAL;
11524
11525 /*
11526 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11527 * Note that pitch changes could also affect these register.
11528 */
11529 if (INTEL_INFO(dev)->gen > 3 &&
11530 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11531 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11532 return -EINVAL;
11533
11534 if (i915_terminally_wedged(&dev_priv->gpu_error))
11535 goto out_hang;
11536
11537 work = kzalloc(sizeof(*work), GFP_KERNEL);
11538 if (work == NULL)
11539 return -ENOMEM;
11540
11541 work->event = event;
11542 work->crtc = crtc;
11543 work->old_fb = old_fb;
11544 INIT_WORK(&work->work, intel_unpin_work_fn);
11545
11546 ret = drm_crtc_vblank_get(crtc);
11547 if (ret)
11548 goto free_work;
11549
11550 /* We borrow the event spin lock for protecting unpin_work */
11551 spin_lock_irq(&dev->event_lock);
11552 if (intel_crtc->unpin_work) {
11553 /* Before declaring the flip queue wedged, check if
11554 * the hardware completed the operation behind our backs.
11555 */
11556 if (__intel_pageflip_stall_check(dev, crtc)) {
11557 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11558 page_flip_completed(intel_crtc);
11559 } else {
11560 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11561 spin_unlock_irq(&dev->event_lock);
11562
11563 drm_crtc_vblank_put(crtc);
11564 kfree(work);
11565 return -EBUSY;
11566 }
11567 }
11568 intel_crtc->unpin_work = work;
11569 spin_unlock_irq(&dev->event_lock);
11570
11571 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11572 flush_workqueue(dev_priv->wq);
11573
11574 /* Reference the objects for the scheduled work. */
11575 drm_framebuffer_reference(work->old_fb);
11576 drm_gem_object_reference(&obj->base);
11577
11578 crtc->primary->fb = fb;
11579 update_state_fb(crtc->primary);
11580
11581 work->pending_flip_obj = obj;
11582
11583 ret = i915_mutex_lock_interruptible(dev);
11584 if (ret)
11585 goto cleanup;
11586
11587 atomic_inc(&intel_crtc->unpin_work_count);
11588 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11589
11590 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11591 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11592
11593 if (IS_VALLEYVIEW(dev)) {
11594 ring = &dev_priv->ring[BCS];
11595 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11596 /* vlv: DISPLAY_FLIP fails to change tiling */
11597 ring = NULL;
11598 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11599 ring = &dev_priv->ring[BCS];
11600 } else if (INTEL_INFO(dev)->gen >= 7) {
11601 ring = i915_gem_request_get_ring(obj->last_write_req);
11602 if (ring == NULL || ring->id != RCS)
11603 ring = &dev_priv->ring[BCS];
11604 } else {
11605 ring = &dev_priv->ring[RCS];
11606 }
11607
11608 mmio_flip = use_mmio_flip(ring, obj);
11609
11610 /* When using CS flips, we want to emit semaphores between rings.
11611 * However, when using mmio flips we will create a task to do the
11612 * synchronisation, so all we want here is to pin the framebuffer
11613 * into the display plane and skip any waits.
11614 */
11615 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11616 crtc->primary->state,
11617 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11618 if (ret)
11619 goto cleanup_pending;
11620
11621 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11622 obj, 0);
11623 work->gtt_offset += intel_crtc->dspaddr_offset;
11624
11625 if (mmio_flip) {
11626 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11627 page_flip_flags);
11628 if (ret)
11629 goto cleanup_unpin;
11630
11631 i915_gem_request_assign(&work->flip_queued_req,
11632 obj->last_write_req);
11633 } else {
11634 if (!request) {
11635 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11636 if (ret)
11637 goto cleanup_unpin;
11638 }
11639
11640 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11641 page_flip_flags);
11642 if (ret)
11643 goto cleanup_unpin;
11644
11645 i915_gem_request_assign(&work->flip_queued_req, request);
11646 }
11647
11648 if (request)
11649 i915_add_request_no_flush(request);
11650
11651 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11652 work->enable_stall_check = true;
11653
11654 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11655 to_intel_plane(primary)->frontbuffer_bit);
11656 mutex_unlock(&dev->struct_mutex);
11657
11658 intel_fbc_disable_crtc(intel_crtc);
11659 intel_frontbuffer_flip_prepare(dev,
11660 to_intel_plane(primary)->frontbuffer_bit);
11661
11662 trace_i915_flip_request(intel_crtc->plane, obj);
11663
11664 return 0;
11665
11666cleanup_unpin:
11667 intel_unpin_fb_obj(fb, crtc->primary->state);
11668cleanup_pending:
11669 if (request)
11670 i915_gem_request_cancel(request);
11671 atomic_dec(&intel_crtc->unpin_work_count);
11672 mutex_unlock(&dev->struct_mutex);
11673cleanup:
11674 crtc->primary->fb = old_fb;
11675 update_state_fb(crtc->primary);
11676
11677 drm_gem_object_unreference_unlocked(&obj->base);
11678 drm_framebuffer_unreference(work->old_fb);
11679
11680 spin_lock_irq(&dev->event_lock);
11681 intel_crtc->unpin_work = NULL;
11682 spin_unlock_irq(&dev->event_lock);
11683
11684 drm_crtc_vblank_put(crtc);
11685free_work:
11686 kfree(work);
11687
11688 if (ret == -EIO) {
11689 struct drm_atomic_state *state;
11690 struct drm_plane_state *plane_state;
11691
11692out_hang:
11693 state = drm_atomic_state_alloc(dev);
11694 if (!state)
11695 return -ENOMEM;
11696 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11697
11698retry:
11699 plane_state = drm_atomic_get_plane_state(state, primary);
11700 ret = PTR_ERR_OR_ZERO(plane_state);
11701 if (!ret) {
11702 drm_atomic_set_fb_for_plane(plane_state, fb);
11703
11704 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11705 if (!ret)
11706 ret = drm_atomic_commit(state);
11707 }
11708
11709 if (ret == -EDEADLK) {
11710 drm_modeset_backoff(state->acquire_ctx);
11711 drm_atomic_state_clear(state);
11712 goto retry;
11713 }
11714
11715 if (ret)
11716 drm_atomic_state_free(state);
11717
11718 if (ret == 0 && event) {
11719 spin_lock_irq(&dev->event_lock);
11720 drm_send_vblank_event(dev, pipe, event);
11721 spin_unlock_irq(&dev->event_lock);
11722 }
11723 }
11724 return ret;
11725}
11726
11727
11728/**
11729 * intel_wm_need_update - Check whether watermarks need updating
11730 * @plane: drm plane
11731 * @state: new plane state
11732 *
11733 * Check current plane state versus the new one to determine whether
11734 * watermarks need to be recalculated.
11735 *
11736 * Returns true or false.
11737 */
11738static bool intel_wm_need_update(struct drm_plane *plane,
11739 struct drm_plane_state *state)
11740{
11741 /* Update watermarks on tiling changes. */
11742 if (!plane->state->fb || !state->fb ||
11743 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11744 plane->state->rotation != state->rotation)
11745 return true;
11746
11747 if (plane->state->crtc_w != state->crtc_w)
11748 return true;
11749
11750 return false;
11751}
11752
11753int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11754 struct drm_plane_state *plane_state)
11755{
11756 struct drm_crtc *crtc = crtc_state->crtc;
11757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11758 struct drm_plane *plane = plane_state->plane;
11759 struct drm_device *dev = crtc->dev;
11760 struct drm_i915_private *dev_priv = dev->dev_private;
11761 struct intel_plane_state *old_plane_state =
11762 to_intel_plane_state(plane->state);
11763 int idx = intel_crtc->base.base.id, ret;
11764 int i = drm_plane_index(plane);
11765 bool mode_changed = needs_modeset(crtc_state);
11766 bool was_crtc_enabled = crtc->state->active;
11767 bool is_crtc_enabled = crtc_state->active;
11768
11769 bool turn_off, turn_on, visible, was_visible;
11770 struct drm_framebuffer *fb = plane_state->fb;
11771
11772 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11773 plane->type != DRM_PLANE_TYPE_CURSOR) {
11774 ret = skl_update_scaler_plane(
11775 to_intel_crtc_state(crtc_state),
11776 to_intel_plane_state(plane_state));
11777 if (ret)
11778 return ret;
11779 }
11780
11781 /*
11782 * Disabling a plane is always okay; we just need to update
11783 * fb tracking in a special way since cleanup_fb() won't
11784 * get called by the plane helpers.
11785 */
11786 if (old_plane_state->base.fb && !fb)
11787 intel_crtc->atomic.disabled_planes |= 1 << i;
11788
11789 was_visible = old_plane_state->visible;
11790 visible = to_intel_plane_state(plane_state)->visible;
11791
11792 if (!was_crtc_enabled && WARN_ON(was_visible))
11793 was_visible = false;
11794
11795 if (!is_crtc_enabled && WARN_ON(visible))
11796 visible = false;
11797
11798 if (!was_visible && !visible)
11799 return 0;
11800
11801 turn_off = was_visible && (!visible || mode_changed);
11802 turn_on = visible && (!was_visible || mode_changed);
11803
11804 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11805 plane->base.id, fb ? fb->base.id : -1);
11806
11807 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11808 plane->base.id, was_visible, visible,
11809 turn_off, turn_on, mode_changed);
11810
11811 if (turn_on) {
11812 intel_crtc->atomic.update_wm_pre = true;
11813 /* must disable cxsr around plane enable/disable */
11814 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11815 intel_crtc->atomic.disable_cxsr = true;
11816 /* to potentially re-enable cxsr */
11817 intel_crtc->atomic.wait_vblank = true;
11818 intel_crtc->atomic.update_wm_post = true;
11819 }
11820 } else if (turn_off) {
11821 intel_crtc->atomic.update_wm_post = true;
11822 /* must disable cxsr around plane enable/disable */
11823 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11824 if (is_crtc_enabled)
11825 intel_crtc->atomic.wait_vblank = true;
11826 intel_crtc->atomic.disable_cxsr = true;
11827 }
11828 } else if (intel_wm_need_update(plane, plane_state)) {
11829 intel_crtc->atomic.update_wm_pre = true;
11830 }
11831
11832 if (visible || was_visible)
11833 intel_crtc->atomic.fb_bits |=
11834 to_intel_plane(plane)->frontbuffer_bit;
11835
11836 switch (plane->type) {
11837 case DRM_PLANE_TYPE_PRIMARY:
11838 intel_crtc->atomic.wait_for_flips = true;
11839 intel_crtc->atomic.pre_disable_primary = turn_off;
11840 intel_crtc->atomic.post_enable_primary = turn_on;
11841
11842 if (turn_off) {
11843 /*
11844 * FIXME: Actually if we will still have any other
11845 * plane enabled on the pipe we could let IPS enabled
11846 * still, but for now lets consider that when we make
11847 * primary invisible by setting DSPCNTR to 0 on
11848 * update_primary_plane function IPS needs to be
11849 * disable.
11850 */
11851 intel_crtc->atomic.disable_ips = true;
11852
11853 intel_crtc->atomic.disable_fbc = true;
11854 }
11855
11856 /*
11857 * FBC does not work on some platforms for rotated
11858 * planes, so disable it when rotation is not 0 and
11859 * update it when rotation is set back to 0.
11860 *
11861 * FIXME: This is redundant with the fbc update done in
11862 * the primary plane enable function except that that
11863 * one is done too late. We eventually need to unify
11864 * this.
11865 */
11866
11867 if (visible &&
11868 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11869 dev_priv->fbc.crtc == intel_crtc &&
11870 plane_state->rotation != BIT(DRM_ROTATE_0))
11871 intel_crtc->atomic.disable_fbc = true;
11872
11873 /*
11874 * BDW signals flip done immediately if the plane
11875 * is disabled, even if the plane enable is already
11876 * armed to occur at the next vblank :(
11877 */
11878 if (turn_on && IS_BROADWELL(dev))
11879 intel_crtc->atomic.wait_vblank = true;
11880
11881 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11882 break;
11883 case DRM_PLANE_TYPE_CURSOR:
11884 break;
11885 case DRM_PLANE_TYPE_OVERLAY:
11886 if (turn_off && !mode_changed) {
11887 intel_crtc->atomic.wait_vblank = true;
11888 intel_crtc->atomic.update_sprite_watermarks |=
11889 1 << i;
11890 }
11891 }
11892 return 0;
11893}
11894
11895static bool encoders_cloneable(const struct intel_encoder *a,
11896 const struct intel_encoder *b)
11897{
11898 /* masks could be asymmetric, so check both ways */
11899 return a == b || (a->cloneable & (1 << b->type) &&
11900 b->cloneable & (1 << a->type));
11901}
11902
11903static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11904 struct intel_crtc *crtc,
11905 struct intel_encoder *encoder)
11906{
11907 struct intel_encoder *source_encoder;
11908 struct drm_connector *connector;
11909 struct drm_connector_state *connector_state;
11910 int i;
11911
11912 for_each_connector_in_state(state, connector, connector_state, i) {
11913 if (connector_state->crtc != &crtc->base)
11914 continue;
11915
11916 source_encoder =
11917 to_intel_encoder(connector_state->best_encoder);
11918 if (!encoders_cloneable(encoder, source_encoder))
11919 return false;
11920 }
11921
11922 return true;
11923}
11924
11925static bool check_encoder_cloning(struct drm_atomic_state *state,
11926 struct intel_crtc *crtc)
11927{
11928 struct intel_encoder *encoder;
11929 struct drm_connector *connector;
11930 struct drm_connector_state *connector_state;
11931 int i;
11932
11933 for_each_connector_in_state(state, connector, connector_state, i) {
11934 if (connector_state->crtc != &crtc->base)
11935 continue;
11936
11937 encoder = to_intel_encoder(connector_state->best_encoder);
11938 if (!check_single_encoder_cloning(state, crtc, encoder))
11939 return false;
11940 }
11941
11942 return true;
11943}
11944
11945static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11946 struct drm_crtc_state *crtc_state)
11947{
11948 struct drm_device *dev = crtc->dev;
11949 struct drm_i915_private *dev_priv = dev->dev_private;
11950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11951 struct intel_crtc_state *pipe_config =
11952 to_intel_crtc_state(crtc_state);
11953 struct drm_atomic_state *state = crtc_state->state;
11954 int ret;
11955 bool mode_changed = needs_modeset(crtc_state);
11956
11957 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11958 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11959 return -EINVAL;
11960 }
11961
11962 if (mode_changed && !crtc_state->active)
11963 intel_crtc->atomic.update_wm_post = true;
11964
11965 if (mode_changed && crtc_state->enable &&
11966 dev_priv->display.crtc_compute_clock &&
11967 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11968 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11969 pipe_config);
11970 if (ret)
11971 return ret;
11972 }
11973
11974 ret = 0;
11975 if (INTEL_INFO(dev)->gen >= 9) {
11976 if (mode_changed)
11977 ret = skl_update_scaler_crtc(pipe_config);
11978
11979 if (!ret)
11980 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11981 pipe_config);
11982 }
11983
11984 return ret;
11985}
11986
11987static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11988 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11989 .load_lut = intel_crtc_load_lut,
11990 .atomic_begin = intel_begin_crtc_commit,
11991 .atomic_flush = intel_finish_crtc_commit,
11992 .atomic_check = intel_crtc_atomic_check,
11993};
11994
11995static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11996{
11997 struct intel_connector *connector;
11998
11999 for_each_intel_connector(dev, connector) {
12000 if (connector->base.encoder) {
12001 connector->base.state->best_encoder =
12002 connector->base.encoder;
12003 connector->base.state->crtc =
12004 connector->base.encoder->crtc;
12005 } else {
12006 connector->base.state->best_encoder = NULL;
12007 connector->base.state->crtc = NULL;
12008 }
12009 }
12010}
12011
12012static void
12013connected_sink_compute_bpp(struct intel_connector *connector,
12014 struct intel_crtc_state *pipe_config)
12015{
12016 int bpp = pipe_config->pipe_bpp;
12017
12018 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12019 connector->base.base.id,
12020 connector->base.name);
12021
12022 /* Don't use an invalid EDID bpc value */
12023 if (connector->base.display_info.bpc &&
12024 connector->base.display_info.bpc * 3 < bpp) {
12025 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12026 bpp, connector->base.display_info.bpc*3);
12027 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12028 }
12029
12030 /* Clamp bpp to 8 on screens without EDID 1.4 */
12031 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12032 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12033 bpp);
12034 pipe_config->pipe_bpp = 24;
12035 }
12036}
12037
12038static int
12039compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12040 struct intel_crtc_state *pipe_config)
12041{
12042 struct drm_device *dev = crtc->base.dev;
12043 struct drm_atomic_state *state;
12044 struct drm_connector *connector;
12045 struct drm_connector_state *connector_state;
12046 int bpp, i;
12047
12048 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12049 bpp = 10*3;
12050 else if (INTEL_INFO(dev)->gen >= 5)
12051 bpp = 12*3;
12052 else
12053 bpp = 8*3;
12054
12055
12056 pipe_config->pipe_bpp = bpp;
12057
12058 state = pipe_config->base.state;
12059
12060 /* Clamp display bpp to EDID value */
12061 for_each_connector_in_state(state, connector, connector_state, i) {
12062 if (connector_state->crtc != &crtc->base)
12063 continue;
12064
12065 connected_sink_compute_bpp(to_intel_connector(connector),
12066 pipe_config);
12067 }
12068
12069 return bpp;
12070}
12071
12072static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12073{
12074 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12075 "type: 0x%x flags: 0x%x\n",
12076 mode->crtc_clock,
12077 mode->crtc_hdisplay, mode->crtc_hsync_start,
12078 mode->crtc_hsync_end, mode->crtc_htotal,
12079 mode->crtc_vdisplay, mode->crtc_vsync_start,
12080 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12081}
12082
12083static void intel_dump_pipe_config(struct intel_crtc *crtc,
12084 struct intel_crtc_state *pipe_config,
12085 const char *context)
12086{
12087 struct drm_device *dev = crtc->base.dev;
12088 struct drm_plane *plane;
12089 struct intel_plane *intel_plane;
12090 struct intel_plane_state *state;
12091 struct drm_framebuffer *fb;
12092
12093 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12094 context, pipe_config, pipe_name(crtc->pipe));
12095
12096 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12097 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12098 pipe_config->pipe_bpp, pipe_config->dither);
12099 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12100 pipe_config->has_pch_encoder,
12101 pipe_config->fdi_lanes,
12102 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12103 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12104 pipe_config->fdi_m_n.tu);
12105 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12106 pipe_config->has_dp_encoder,
12107 pipe_config->lane_count,
12108 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12109 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12110 pipe_config->dp_m_n.tu);
12111
12112 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12113 pipe_config->has_dp_encoder,
12114 pipe_config->lane_count,
12115 pipe_config->dp_m2_n2.gmch_m,
12116 pipe_config->dp_m2_n2.gmch_n,
12117 pipe_config->dp_m2_n2.link_m,
12118 pipe_config->dp_m2_n2.link_n,
12119 pipe_config->dp_m2_n2.tu);
12120
12121 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12122 pipe_config->has_audio,
12123 pipe_config->has_infoframe);
12124
12125 DRM_DEBUG_KMS("requested mode:\n");
12126 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12127 DRM_DEBUG_KMS("adjusted mode:\n");
12128 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12129 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12130 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12131 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12132 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12133 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12134 crtc->num_scalers,
12135 pipe_config->scaler_state.scaler_users,
12136 pipe_config->scaler_state.scaler_id);
12137 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12138 pipe_config->gmch_pfit.control,
12139 pipe_config->gmch_pfit.pgm_ratios,
12140 pipe_config->gmch_pfit.lvds_border_bits);
12141 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12142 pipe_config->pch_pfit.pos,
12143 pipe_config->pch_pfit.size,
12144 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12145 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12146 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12147
12148 if (IS_BROXTON(dev)) {
12149 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12150 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12151 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12152 pipe_config->ddi_pll_sel,
12153 pipe_config->dpll_hw_state.ebb0,
12154 pipe_config->dpll_hw_state.ebb4,
12155 pipe_config->dpll_hw_state.pll0,
12156 pipe_config->dpll_hw_state.pll1,
12157 pipe_config->dpll_hw_state.pll2,
12158 pipe_config->dpll_hw_state.pll3,
12159 pipe_config->dpll_hw_state.pll6,
12160 pipe_config->dpll_hw_state.pll8,
12161 pipe_config->dpll_hw_state.pll9,
12162 pipe_config->dpll_hw_state.pll10,
12163 pipe_config->dpll_hw_state.pcsdw12);
12164 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12165 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12166 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12167 pipe_config->ddi_pll_sel,
12168 pipe_config->dpll_hw_state.ctrl1,
12169 pipe_config->dpll_hw_state.cfgcr1,
12170 pipe_config->dpll_hw_state.cfgcr2);
12171 } else if (HAS_DDI(dev)) {
12172 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12173 pipe_config->ddi_pll_sel,
12174 pipe_config->dpll_hw_state.wrpll,
12175 pipe_config->dpll_hw_state.spll);
12176 } else {
12177 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12178 "fp0: 0x%x, fp1: 0x%x\n",
12179 pipe_config->dpll_hw_state.dpll,
12180 pipe_config->dpll_hw_state.dpll_md,
12181 pipe_config->dpll_hw_state.fp0,
12182 pipe_config->dpll_hw_state.fp1);
12183 }
12184
12185 DRM_DEBUG_KMS("planes on this crtc\n");
12186 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12187 intel_plane = to_intel_plane(plane);
12188 if (intel_plane->pipe != crtc->pipe)
12189 continue;
12190
12191 state = to_intel_plane_state(plane->state);
12192 fb = state->base.fb;
12193 if (!fb) {
12194 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12195 "disabled, scaler_id = %d\n",
12196 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12197 plane->base.id, intel_plane->pipe,
12198 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12199 drm_plane_index(plane), state->scaler_id);
12200 continue;
12201 }
12202
12203 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12204 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12205 plane->base.id, intel_plane->pipe,
12206 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12207 drm_plane_index(plane));
12208 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12209 fb->base.id, fb->width, fb->height, fb->pixel_format);
12210 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12211 state->scaler_id,
12212 state->src.x1 >> 16, state->src.y1 >> 16,
12213 drm_rect_width(&state->src) >> 16,
12214 drm_rect_height(&state->src) >> 16,
12215 state->dst.x1, state->dst.y1,
12216 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12217 }
12218}
12219
12220static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12221{
12222 struct drm_device *dev = state->dev;
12223 struct drm_connector *connector;
12224 unsigned int used_ports = 0;
12225
12226 /*
12227 * Walk the connector list instead of the encoder
12228 * list to detect the problem on ddi platforms
12229 * where there's just one encoder per digital port.
12230 */
12231 drm_for_each_connector(connector, dev) {
12232 struct drm_connector_state *connector_state;
12233 struct intel_encoder *encoder;
12234
12235 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12236 if (!connector_state)
12237 connector_state = connector->state;
12238
12239 if (!connector_state->best_encoder)
12240 continue;
12241
12242 encoder = to_intel_encoder(connector_state->best_encoder);
12243
12244 WARN_ON(!connector_state->crtc);
12245
12246 switch (encoder->type) {
12247 unsigned int port_mask;
12248 case INTEL_OUTPUT_UNKNOWN:
12249 if (WARN_ON(!HAS_DDI(dev)))
12250 break;
12251 case INTEL_OUTPUT_DISPLAYPORT:
12252 case INTEL_OUTPUT_HDMI:
12253 case INTEL_OUTPUT_EDP:
12254 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12255
12256 /* the same port mustn't appear more than once */
12257 if (used_ports & port_mask)
12258 return false;
12259
12260 used_ports |= port_mask;
12261 default:
12262 break;
12263 }
12264 }
12265
12266 return true;
12267}
12268
12269static void
12270clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12271{
12272 struct drm_crtc_state tmp_state;
12273 struct intel_crtc_scaler_state scaler_state;
12274 struct intel_dpll_hw_state dpll_hw_state;
12275 enum intel_dpll_id shared_dpll;
12276 uint32_t ddi_pll_sel;
12277 bool force_thru;
12278
12279 /* FIXME: before the switch to atomic started, a new pipe_config was
12280 * kzalloc'd. Code that depends on any field being zero should be
12281 * fixed, so that the crtc_state can be safely duplicated. For now,
12282 * only fields that are know to not cause problems are preserved. */
12283
12284 tmp_state = crtc_state->base;
12285 scaler_state = crtc_state->scaler_state;
12286 shared_dpll = crtc_state->shared_dpll;
12287 dpll_hw_state = crtc_state->dpll_hw_state;
12288 ddi_pll_sel = crtc_state->ddi_pll_sel;
12289 force_thru = crtc_state->pch_pfit.force_thru;
12290
12291 memset(crtc_state, 0, sizeof *crtc_state);
12292
12293 crtc_state->base = tmp_state;
12294 crtc_state->scaler_state = scaler_state;
12295 crtc_state->shared_dpll = shared_dpll;
12296 crtc_state->dpll_hw_state = dpll_hw_state;
12297 crtc_state->ddi_pll_sel = ddi_pll_sel;
12298 crtc_state->pch_pfit.force_thru = force_thru;
12299}
12300
12301static int
12302intel_modeset_pipe_config(struct drm_crtc *crtc,
12303 struct intel_crtc_state *pipe_config)
12304{
12305 struct drm_atomic_state *state = pipe_config->base.state;
12306 struct intel_encoder *encoder;
12307 struct drm_connector *connector;
12308 struct drm_connector_state *connector_state;
12309 int base_bpp, ret = -EINVAL;
12310 int i;
12311 bool retry = true;
12312
12313 clear_intel_crtc_state(pipe_config);
12314
12315 pipe_config->cpu_transcoder =
12316 (enum transcoder) to_intel_crtc(crtc)->pipe;
12317
12318 /*
12319 * Sanitize sync polarity flags based on requested ones. If neither
12320 * positive or negative polarity is requested, treat this as meaning
12321 * negative polarity.
12322 */
12323 if (!(pipe_config->base.adjusted_mode.flags &
12324 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12325 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12326
12327 if (!(pipe_config->base.adjusted_mode.flags &
12328 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12329 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12330
12331 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12332 pipe_config);
12333 if (base_bpp < 0)
12334 goto fail;
12335
12336 /*
12337 * Determine the real pipe dimensions. Note that stereo modes can
12338 * increase the actual pipe size due to the frame doubling and
12339 * insertion of additional space for blanks between the frame. This
12340 * is stored in the crtc timings. We use the requested mode to do this
12341 * computation to clearly distinguish it from the adjusted mode, which
12342 * can be changed by the connectors in the below retry loop.
12343 */
12344 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12345 &pipe_config->pipe_src_w,
12346 &pipe_config->pipe_src_h);
12347
12348encoder_retry:
12349 /* Ensure the port clock defaults are reset when retrying. */
12350 pipe_config->port_clock = 0;
12351 pipe_config->pixel_multiplier = 1;
12352
12353 /* Fill in default crtc timings, allow encoders to overwrite them. */
12354 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12355 CRTC_STEREO_DOUBLE);
12356
12357 /* Pass our mode to the connectors and the CRTC to give them a chance to
12358 * adjust it according to limitations or connector properties, and also
12359 * a chance to reject the mode entirely.
12360 */
12361 for_each_connector_in_state(state, connector, connector_state, i) {
12362 if (connector_state->crtc != crtc)
12363 continue;
12364
12365 encoder = to_intel_encoder(connector_state->best_encoder);
12366
12367 if (!(encoder->compute_config(encoder, pipe_config))) {
12368 DRM_DEBUG_KMS("Encoder config failure\n");
12369 goto fail;
12370 }
12371 }
12372
12373 /* Set default port clock if not overwritten by the encoder. Needs to be
12374 * done afterwards in case the encoder adjusts the mode. */
12375 if (!pipe_config->port_clock)
12376 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12377 * pipe_config->pixel_multiplier;
12378
12379 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12380 if (ret < 0) {
12381 DRM_DEBUG_KMS("CRTC fixup failed\n");
12382 goto fail;
12383 }
12384
12385 if (ret == RETRY) {
12386 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12387 ret = -EINVAL;
12388 goto fail;
12389 }
12390
12391 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12392 retry = false;
12393 goto encoder_retry;
12394 }
12395
12396 /* Dithering seems to not pass-through bits correctly when it should, so
12397 * only enable it on 6bpc panels. */
12398 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12399 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12400 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12401
12402fail:
12403 return ret;
12404}
12405
12406static void
12407intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12408{
12409 struct drm_crtc *crtc;
12410 struct drm_crtc_state *crtc_state;
12411 int i;
12412
12413 /* Double check state. */
12414 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12415 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12416
12417 /* Update hwmode for vblank functions */
12418 if (crtc->state->active)
12419 crtc->hwmode = crtc->state->adjusted_mode;
12420 else
12421 crtc->hwmode.crtc_clock = 0;
12422 }
12423}
12424
12425static bool intel_fuzzy_clock_check(int clock1, int clock2)
12426{
12427 int diff;
12428
12429 if (clock1 == clock2)
12430 return true;
12431
12432 if (!clock1 || !clock2)
12433 return false;
12434
12435 diff = abs(clock1 - clock2);
12436
12437 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12438 return true;
12439
12440 return false;
12441}
12442
12443#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12444 list_for_each_entry((intel_crtc), \
12445 &(dev)->mode_config.crtc_list, \
12446 base.head) \
12447 if (mask & (1 <<(intel_crtc)->pipe))
12448
12449static bool
12450intel_compare_m_n(unsigned int m, unsigned int n,
12451 unsigned int m2, unsigned int n2,
12452 bool exact)
12453{
12454 if (m == m2 && n == n2)
12455 return true;
12456
12457 if (exact || !m || !n || !m2 || !n2)
12458 return false;
12459
12460 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12461
12462 if (m > m2) {
12463 while (m > m2) {
12464 m2 <<= 1;
12465 n2 <<= 1;
12466 }
12467 } else if (m < m2) {
12468 while (m < m2) {
12469 m <<= 1;
12470 n <<= 1;
12471 }
12472 }
12473
12474 return m == m2 && n == n2;
12475}
12476
12477static bool
12478intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12479 struct intel_link_m_n *m2_n2,
12480 bool adjust)
12481{
12482 if (m_n->tu == m2_n2->tu &&
12483 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12484 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12485 intel_compare_m_n(m_n->link_m, m_n->link_n,
12486 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12487 if (adjust)
12488 *m2_n2 = *m_n;
12489
12490 return true;
12491 }
12492
12493 return false;
12494}
12495
12496static bool
12497intel_pipe_config_compare(struct drm_device *dev,
12498 struct intel_crtc_state *current_config,
12499 struct intel_crtc_state *pipe_config,
12500 bool adjust)
12501{
12502 bool ret = true;
12503
12504#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12505 do { \
12506 if (!adjust) \
12507 DRM_ERROR(fmt, ##__VA_ARGS__); \
12508 else \
12509 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12510 } while (0)
12511
12512#define PIPE_CONF_CHECK_X(name) \
12513 if (current_config->name != pipe_config->name) { \
12514 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12515 "(expected 0x%08x, found 0x%08x)\n", \
12516 current_config->name, \
12517 pipe_config->name); \
12518 ret = false; \
12519 }
12520
12521#define PIPE_CONF_CHECK_I(name) \
12522 if (current_config->name != pipe_config->name) { \
12523 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12524 "(expected %i, found %i)\n", \
12525 current_config->name, \
12526 pipe_config->name); \
12527 ret = false; \
12528 }
12529
12530#define PIPE_CONF_CHECK_M_N(name) \
12531 if (!intel_compare_link_m_n(&current_config->name, \
12532 &pipe_config->name,\
12533 adjust)) { \
12534 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12535 "(expected tu %i gmch %i/%i link %i/%i, " \
12536 "found tu %i, gmch %i/%i link %i/%i)\n", \
12537 current_config->name.tu, \
12538 current_config->name.gmch_m, \
12539 current_config->name.gmch_n, \
12540 current_config->name.link_m, \
12541 current_config->name.link_n, \
12542 pipe_config->name.tu, \
12543 pipe_config->name.gmch_m, \
12544 pipe_config->name.gmch_n, \
12545 pipe_config->name.link_m, \
12546 pipe_config->name.link_n); \
12547 ret = false; \
12548 }
12549
12550#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12551 if (!intel_compare_link_m_n(&current_config->name, \
12552 &pipe_config->name, adjust) && \
12553 !intel_compare_link_m_n(&current_config->alt_name, \
12554 &pipe_config->name, adjust)) { \
12555 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12556 "(expected tu %i gmch %i/%i link %i/%i, " \
12557 "or tu %i gmch %i/%i link %i/%i, " \
12558 "found tu %i, gmch %i/%i link %i/%i)\n", \
12559 current_config->name.tu, \
12560 current_config->name.gmch_m, \
12561 current_config->name.gmch_n, \
12562 current_config->name.link_m, \
12563 current_config->name.link_n, \
12564 current_config->alt_name.tu, \
12565 current_config->alt_name.gmch_m, \
12566 current_config->alt_name.gmch_n, \
12567 current_config->alt_name.link_m, \
12568 current_config->alt_name.link_n, \
12569 pipe_config->name.tu, \
12570 pipe_config->name.gmch_m, \
12571 pipe_config->name.gmch_n, \
12572 pipe_config->name.link_m, \
12573 pipe_config->name.link_n); \
12574 ret = false; \
12575 }
12576
12577/* This is required for BDW+ where there is only one set of registers for
12578 * switching between high and low RR.
12579 * This macro can be used whenever a comparison has to be made between one
12580 * hw state and multiple sw state variables.
12581 */
12582#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12583 if ((current_config->name != pipe_config->name) && \
12584 (current_config->alt_name != pipe_config->name)) { \
12585 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12586 "(expected %i or %i, found %i)\n", \
12587 current_config->name, \
12588 current_config->alt_name, \
12589 pipe_config->name); \
12590 ret = false; \
12591 }
12592
12593#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12594 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12595 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12596 "(expected %i, found %i)\n", \
12597 current_config->name & (mask), \
12598 pipe_config->name & (mask)); \
12599 ret = false; \
12600 }
12601
12602#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12603 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12604 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12605 "(expected %i, found %i)\n", \
12606 current_config->name, \
12607 pipe_config->name); \
12608 ret = false; \
12609 }
12610
12611#define PIPE_CONF_QUIRK(quirk) \
12612 ((current_config->quirks | pipe_config->quirks) & (quirk))
12613
12614 PIPE_CONF_CHECK_I(cpu_transcoder);
12615
12616 PIPE_CONF_CHECK_I(has_pch_encoder);
12617 PIPE_CONF_CHECK_I(fdi_lanes);
12618 PIPE_CONF_CHECK_M_N(fdi_m_n);
12619
12620 PIPE_CONF_CHECK_I(has_dp_encoder);
12621 PIPE_CONF_CHECK_I(lane_count);
12622
12623 if (INTEL_INFO(dev)->gen < 8) {
12624 PIPE_CONF_CHECK_M_N(dp_m_n);
12625
12626 if (current_config->has_drrs)
12627 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12628 } else
12629 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12630
12631 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12632 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12633 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12634 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12635 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12636 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12637
12638 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12639 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12640 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12641 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12642 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12643 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12644
12645 PIPE_CONF_CHECK_I(pixel_multiplier);
12646 PIPE_CONF_CHECK_I(has_hdmi_sink);
12647 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12648 IS_VALLEYVIEW(dev))
12649 PIPE_CONF_CHECK_I(limited_color_range);
12650 PIPE_CONF_CHECK_I(has_infoframe);
12651
12652 PIPE_CONF_CHECK_I(has_audio);
12653
12654 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12655 DRM_MODE_FLAG_INTERLACE);
12656
12657 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12658 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12659 DRM_MODE_FLAG_PHSYNC);
12660 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12661 DRM_MODE_FLAG_NHSYNC);
12662 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12663 DRM_MODE_FLAG_PVSYNC);
12664 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12665 DRM_MODE_FLAG_NVSYNC);
12666 }
12667
12668 PIPE_CONF_CHECK_X(gmch_pfit.control);
12669 /* pfit ratios are autocomputed by the hw on gen4+ */
12670 if (INTEL_INFO(dev)->gen < 4)
12671 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12672 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12673
12674 if (!adjust) {
12675 PIPE_CONF_CHECK_I(pipe_src_w);
12676 PIPE_CONF_CHECK_I(pipe_src_h);
12677
12678 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12679 if (current_config->pch_pfit.enabled) {
12680 PIPE_CONF_CHECK_X(pch_pfit.pos);
12681 PIPE_CONF_CHECK_X(pch_pfit.size);
12682 }
12683
12684 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12685 }
12686
12687 /* BDW+ don't expose a synchronous way to read the state */
12688 if (IS_HASWELL(dev))
12689 PIPE_CONF_CHECK_I(ips_enabled);
12690
12691 PIPE_CONF_CHECK_I(double_wide);
12692
12693 PIPE_CONF_CHECK_X(ddi_pll_sel);
12694
12695 PIPE_CONF_CHECK_I(shared_dpll);
12696 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12697 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12698 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12699 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12700 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12701 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12702 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12703 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12704 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12705
12706 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12707 PIPE_CONF_CHECK_I(pipe_bpp);
12708
12709 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12710 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12711
12712#undef PIPE_CONF_CHECK_X
12713#undef PIPE_CONF_CHECK_I
12714#undef PIPE_CONF_CHECK_I_ALT
12715#undef PIPE_CONF_CHECK_FLAGS
12716#undef PIPE_CONF_CHECK_CLOCK_FUZZY
12717#undef PIPE_CONF_QUIRK
12718#undef INTEL_ERR_OR_DBG_KMS
12719
12720 return ret;
12721}
12722
12723static void check_wm_state(struct drm_device *dev)
12724{
12725 struct drm_i915_private *dev_priv = dev->dev_private;
12726 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12727 struct intel_crtc *intel_crtc;
12728 int plane;
12729
12730 if (INTEL_INFO(dev)->gen < 9)
12731 return;
12732
12733 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12734 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12735
12736 for_each_intel_crtc(dev, intel_crtc) {
12737 struct skl_ddb_entry *hw_entry, *sw_entry;
12738 const enum i915_pipe pipe = intel_crtc->pipe;
12739
12740 if (!intel_crtc->active)
12741 continue;
12742
12743 /* planes */
12744 for_each_plane(dev_priv, pipe, plane) {
12745 hw_entry = &hw_ddb.plane[pipe][plane];
12746 sw_entry = &sw_ddb->plane[pipe][plane];
12747
12748 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12749 continue;
12750
12751 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12752 "(expected (%u,%u), found (%u,%u))\n",
12753 pipe_name(pipe), plane + 1,
12754 sw_entry->start, sw_entry->end,
12755 hw_entry->start, hw_entry->end);
12756 }
12757
12758 /* cursor */
12759 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12760 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12761
12762 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12763 continue;
12764
12765 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12766 "(expected (%u,%u), found (%u,%u))\n",
12767 pipe_name(pipe),
12768 sw_entry->start, sw_entry->end,
12769 hw_entry->start, hw_entry->end);
12770 }
12771}
12772
12773static void
12774check_connector_state(struct drm_device *dev,
12775 struct drm_atomic_state *old_state)
12776{
12777 struct drm_connector_state *old_conn_state __unused;
12778 struct drm_connector *connector;
12779 int i;
12780
12781 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12782 struct drm_encoder *encoder = connector->encoder;
12783 struct drm_connector_state *state = connector->state;
12784
12785 /* This also checks the encoder/connector hw state with the
12786 * ->get_hw_state callbacks. */
12787 intel_connector_check_state(to_intel_connector(connector));
12788
12789 I915_STATE_WARN(state->best_encoder != encoder,
12790 "connector's atomic encoder doesn't match legacy encoder\n");
12791 }
12792}
12793
12794static void
12795check_encoder_state(struct drm_device *dev)
12796{
12797 struct intel_encoder *encoder;
12798 struct intel_connector *connector;
12799
12800 for_each_intel_encoder(dev, encoder) {
12801 bool enabled = false;
12802 enum i915_pipe pipe;
12803
12804 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12805 encoder->base.base.id,
12806 encoder->base.name);
12807
12808 for_each_intel_connector(dev, connector) {
12809 if (connector->base.state->best_encoder != &encoder->base)
12810 continue;
12811 enabled = true;
12812
12813 I915_STATE_WARN(connector->base.state->crtc !=
12814 encoder->base.crtc,
12815 "connector's crtc doesn't match encoder crtc\n");
12816 }
12817
12818 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12819 "encoder's enabled state mismatch "
12820 "(expected %i, found %i)\n",
12821 !!encoder->base.crtc, enabled);
12822
12823 if (!encoder->base.crtc) {
12824 bool active;
12825
12826 active = encoder->get_hw_state(encoder, &pipe);
12827 I915_STATE_WARN(active,
12828 "encoder detached but still enabled on pipe %c.\n",
12829 pipe_name(pipe));
12830 }
12831 }
12832}
12833
12834static void
12835check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12836{
12837 struct drm_i915_private *dev_priv = dev->dev_private;
12838 struct intel_encoder *encoder;
12839 struct drm_crtc_state *old_crtc_state;
12840 struct drm_crtc *crtc;
12841 int i;
12842
12843 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12845 struct intel_crtc_state *pipe_config, *sw_config;
12846 bool active;
12847
12848 if (!needs_modeset(crtc->state) &&
12849 !to_intel_crtc_state(crtc->state)->update_pipe)
12850 continue;
12851
12852 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12853 pipe_config = to_intel_crtc_state(old_crtc_state);
12854 memset(pipe_config, 0, sizeof(*pipe_config));
12855 pipe_config->base.crtc = crtc;
12856 pipe_config->base.state = old_state;
12857
12858 DRM_DEBUG_KMS("[CRTC:%d]\n",
12859 crtc->base.id);
12860
12861 active = dev_priv->display.get_pipe_config(intel_crtc,
12862 pipe_config);
12863
12864 /* hw state is inconsistent with the pipe quirk */
12865 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12866 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12867 active = crtc->state->active;
12868
12869 I915_STATE_WARN(crtc->state->active != active,
12870 "crtc active state doesn't match with hw state "
12871 "(expected %i, found %i)\n", crtc->state->active, active);
12872
12873 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12874 "transitional active state does not match atomic hw state "
12875 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12876
12877 for_each_encoder_on_crtc(dev, crtc, encoder) {
12878 enum i915_pipe pipe;
12879
12880 active = encoder->get_hw_state(encoder, &pipe);
12881 I915_STATE_WARN(active != crtc->state->active,
12882 "[ENCODER:%i] active %i with crtc active %i\n",
12883 encoder->base.base.id, active, crtc->state->active);
12884
12885 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12886 "Encoder connected to wrong pipe %c\n",
12887 pipe_name(pipe));
12888
12889 if (active)
12890 encoder->get_config(encoder, pipe_config);
12891 }
12892
12893 if (!crtc->state->active)
12894 continue;
12895
12896 sw_config = to_intel_crtc_state(crtc->state);
12897 if (!intel_pipe_config_compare(dev, sw_config,
12898 pipe_config, false)) {
12899 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12900 intel_dump_pipe_config(intel_crtc, pipe_config,
12901 "[hw state]");
12902 intel_dump_pipe_config(intel_crtc, sw_config,
12903 "[sw state]");
12904 }
12905 }
12906}
12907
12908static void
12909check_shared_dpll_state(struct drm_device *dev)
12910{
12911 struct drm_i915_private *dev_priv = dev->dev_private;
12912 struct intel_crtc *crtc;
12913 struct intel_dpll_hw_state dpll_hw_state;
12914 int i;
12915
12916 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12917 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12918 int enabled_crtcs = 0, active_crtcs = 0;
12919 bool active;
12920
12921 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12922
12923 DRM_DEBUG_KMS("%s\n", pll->name);
12924
12925 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12926
12927 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12928 "more active pll users than references: %i vs %i\n",
12929 pll->active, hweight32(pll->config.crtc_mask));
12930 I915_STATE_WARN(pll->active && !pll->on,
12931 "pll in active use but not on in sw tracking\n");
12932 I915_STATE_WARN(pll->on && !pll->active,
12933 "pll in on but not on in use in sw tracking\n");
12934 I915_STATE_WARN(pll->on != active,
12935 "pll on state mismatch (expected %i, found %i)\n",
12936 pll->on, active);
12937
12938 for_each_intel_crtc(dev, crtc) {
12939 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12940 enabled_crtcs++;
12941 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12942 active_crtcs++;
12943 }
12944 I915_STATE_WARN(pll->active != active_crtcs,
12945 "pll active crtcs mismatch (expected %i, found %i)\n",
12946 pll->active, active_crtcs);
12947 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12948 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12949 hweight32(pll->config.crtc_mask), enabled_crtcs);
12950
12951 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12952 sizeof(dpll_hw_state)),
12953 "pll hw state mismatch\n");
12954 }
12955}
12956
12957static void
12958intel_modeset_check_state(struct drm_device *dev,
12959 struct drm_atomic_state *old_state)
12960{
12961 check_wm_state(dev);
12962 check_connector_state(dev, old_state);
12963 check_encoder_state(dev);
12964 check_crtc_state(dev, old_state);
12965 check_shared_dpll_state(dev);
12966}
12967
12968void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12969 int dotclock)
12970{
12971 /*
12972 * FDI already provided one idea for the dotclock.
12973 * Yell if the encoder disagrees.
12974 */
12975 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12976 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12977 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12978}
12979
12980static void update_scanline_offset(struct intel_crtc *crtc)
12981{
12982 struct drm_device *dev = crtc->base.dev;
12983
12984 /*
12985 * The scanline counter increments at the leading edge of hsync.
12986 *
12987 * On most platforms it starts counting from vtotal-1 on the
12988 * first active line. That means the scanline counter value is
12989 * always one less than what we would expect. Ie. just after
12990 * start of vblank, which also occurs at start of hsync (on the
12991 * last active line), the scanline counter will read vblank_start-1.
12992 *
12993 * On gen2 the scanline counter starts counting from 1 instead
12994 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12995 * to keep the value positive), instead of adding one.
12996 *
12997 * On HSW+ the behaviour of the scanline counter depends on the output
12998 * type. For DP ports it behaves like most other platforms, but on HDMI
12999 * there's an extra 1 line difference. So we need to add two instead of
13000 * one to the value.
13001 */
13002 if (IS_GEN2(dev)) {
13003 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13004 int vtotal;
13005
13006 vtotal = adjusted_mode->crtc_vtotal;
13007 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13008 vtotal /= 2;
13009
13010 crtc->scanline_offset = vtotal - 1;
13011 } else if (HAS_DDI(dev) &&
13012 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13013 crtc->scanline_offset = 2;
13014 } else
13015 crtc->scanline_offset = 1;
13016}
13017
13018static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13019{
13020 struct drm_device *dev = state->dev;
13021 struct drm_i915_private *dev_priv = to_i915(dev);
13022 struct intel_shared_dpll_config *shared_dpll = NULL;
13023 struct intel_crtc *intel_crtc;
13024 struct intel_crtc_state *intel_crtc_state;
13025 struct drm_crtc *crtc;
13026 struct drm_crtc_state *crtc_state;
13027 int i;
13028
13029 if (!dev_priv->display.crtc_compute_clock)
13030 return;
13031
13032 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13033 int dpll;
13034
13035 intel_crtc = to_intel_crtc(crtc);
13036 intel_crtc_state = to_intel_crtc_state(crtc_state);
13037 dpll = intel_crtc_state->shared_dpll;
13038
13039 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13040 continue;
13041
13042 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13043
13044 if (!shared_dpll)
13045 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13046
13047 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13048 }
13049}
13050
13051/*
13052 * This implements the workaround described in the "notes" section of the mode
13053 * set sequence documentation. When going from no pipes or single pipe to
13054 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13055 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13056 */
13057static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13058{
13059 struct drm_crtc_state *crtc_state;
13060 struct intel_crtc *intel_crtc;
13061 struct drm_crtc *crtc;
13062 struct intel_crtc_state *first_crtc_state = NULL;
13063 struct intel_crtc_state *other_crtc_state = NULL;
13064 enum i915_pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13065 int i;
13066
13067 /* look at all crtc's that are going to be enabled in during modeset */
13068 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13069 intel_crtc = to_intel_crtc(crtc);
13070
13071 if (!crtc_state->active || !needs_modeset(crtc_state))
13072 continue;
13073
13074 if (first_crtc_state) {
13075 other_crtc_state = to_intel_crtc_state(crtc_state);
13076 break;
13077 } else {
13078 first_crtc_state = to_intel_crtc_state(crtc_state);
13079 first_pipe = intel_crtc->pipe;
13080 }
13081 }
13082
13083 /* No workaround needed? */
13084 if (!first_crtc_state)
13085 return 0;
13086
13087 /* w/a possibly needed, check how many crtc's are already enabled. */
13088 for_each_intel_crtc(state->dev, intel_crtc) {
13089 struct intel_crtc_state *pipe_config;
13090
13091 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13092 if (IS_ERR(pipe_config))
13093 return PTR_ERR(pipe_config);
13094
13095 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13096
13097 if (!pipe_config->base.active ||
13098 needs_modeset(&pipe_config->base))
13099 continue;
13100
13101 /* 2 or more enabled crtcs means no need for w/a */
13102 if (enabled_pipe != INVALID_PIPE)
13103 return 0;
13104
13105 enabled_pipe = intel_crtc->pipe;
13106 }
13107
13108 if (enabled_pipe != INVALID_PIPE)
13109 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13110 else if (other_crtc_state)
13111 other_crtc_state->hsw_workaround_pipe = first_pipe;
13112
13113 return 0;
13114}
13115
13116static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13117{
13118 struct drm_crtc *crtc;
13119 struct drm_crtc_state *crtc_state;
13120 int ret = 0;
13121
13122 /* add all active pipes to the state */
13123 for_each_crtc(state->dev, crtc) {
13124 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13125 if (IS_ERR(crtc_state))
13126 return PTR_ERR(crtc_state);
13127
13128 if (!crtc_state->active || needs_modeset(crtc_state))
13129 continue;
13130
13131 crtc_state->mode_changed = true;
13132
13133 ret = drm_atomic_add_affected_connectors(state, crtc);
13134 if (ret)
13135 break;
13136
13137 ret = drm_atomic_add_affected_planes(state, crtc);
13138 if (ret)
13139 break;
13140 }
13141
13142 return ret;
13143}
13144
13145static int intel_modeset_checks(struct drm_atomic_state *state)
13146{
13147 struct drm_device *dev = state->dev;
13148 struct drm_i915_private *dev_priv = dev->dev_private;
13149 int ret;
13150
13151 if (!check_digital_port_conflicts(state)) {
13152 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13153 return -EINVAL;
13154 }
13155
13156 /*
13157 * See if the config requires any additional preparation, e.g.
13158 * to adjust global state with pipes off. We need to do this
13159 * here so we can get the modeset_pipe updated config for the new
13160 * mode set on this crtc. For other crtcs we need to use the
13161 * adjusted_mode bits in the crtc directly.
13162 */
13163 if (dev_priv->display.modeset_calc_cdclk) {
13164 unsigned int cdclk;
13165
13166 ret = dev_priv->display.modeset_calc_cdclk(state);
13167
13168 cdclk = to_intel_atomic_state(state)->cdclk;
13169 if (!ret && cdclk != dev_priv->cdclk_freq)
13170 ret = intel_modeset_all_pipes(state);
13171
13172 if (ret < 0)
13173 return ret;
13174 } else
13175 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13176
13177 intel_modeset_clear_plls(state);
13178
13179 if (IS_HASWELL(dev))
13180 return haswell_mode_set_planes_workaround(state);
13181
13182 return 0;
13183}
13184
13185/**
13186 * intel_atomic_check - validate state object
13187 * @dev: drm device
13188 * @state: state to validate
13189 */
13190static int intel_atomic_check(struct drm_device *dev,
13191 struct drm_atomic_state *state)
13192{
13193 struct drm_crtc *crtc;
13194 struct drm_crtc_state *crtc_state;
13195 int ret, i;
13196 bool any_ms = false;
13197
13198 ret = drm_atomic_helper_check_modeset(dev, state);
13199 if (ret)
13200 return ret;
13201
13202 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13203 struct intel_crtc_state *pipe_config =
13204 to_intel_crtc_state(crtc_state);
13205
13206 memset(&to_intel_crtc(crtc)->atomic, 0,
13207 sizeof(struct intel_crtc_atomic_commit));
13208
13209 /* Catch I915_MODE_FLAG_INHERITED */
13210 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13211 crtc_state->mode_changed = true;
13212
13213 if (!crtc_state->enable) {
13214 if (needs_modeset(crtc_state))
13215 any_ms = true;
13216 continue;
13217 }
13218
13219 if (!needs_modeset(crtc_state))
13220 continue;
13221
13222 /* FIXME: For only active_changed we shouldn't need to do any
13223 * state recomputation at all. */
13224
13225 ret = drm_atomic_add_affected_connectors(state, crtc);
13226 if (ret)
13227 return ret;
13228
13229 ret = intel_modeset_pipe_config(crtc, pipe_config);
13230 if (ret)
13231 return ret;
13232
13233 if (i915.fastboot &&
13234 intel_pipe_config_compare(state->dev,
13235 to_intel_crtc_state(crtc->state),
13236 pipe_config, true)) {
13237 crtc_state->mode_changed = false;
13238 to_intel_crtc_state(crtc_state)->update_pipe = true;
13239 }
13240
13241 if (needs_modeset(crtc_state)) {
13242 any_ms = true;
13243
13244 ret = drm_atomic_add_affected_planes(state, crtc);
13245 if (ret)
13246 return ret;
13247 }
13248
13249 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13250 needs_modeset(crtc_state) ?
13251 "[modeset]" : "[fastset]");
13252 }
13253
13254 if (any_ms) {
13255 ret = intel_modeset_checks(state);
13256
13257 if (ret)
13258 return ret;
13259 } else
13260 to_intel_atomic_state(state)->cdclk =
13261 to_i915(state->dev)->cdclk_freq;
13262
13263 return drm_atomic_helper_check_planes(state->dev, state);
13264}
13265
13266/**
13267 * intel_atomic_commit - commit validated state object
13268 * @dev: DRM device
13269 * @state: the top-level driver state object
13270 * @async: asynchronous commit
13271 *
13272 * This function commits a top-level state object that has been validated
13273 * with drm_atomic_helper_check().
13274 *
13275 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13276 * we can only handle plane-related operations and do not yet support
13277 * asynchronous commit.
13278 *
13279 * RETURNS
13280 * Zero for success or -errno.
13281 */
13282static int intel_atomic_commit(struct drm_device *dev,
13283 struct drm_atomic_state *state,
13284 bool async)
13285{
13286 struct drm_i915_private *dev_priv = dev->dev_private;
13287 struct drm_crtc *crtc;
13288 struct drm_crtc_state *crtc_state;
13289 int ret = 0;
13290 int i;
13291 bool any_ms = false;
13292
13293 if (async) {
13294 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13295 return -EINVAL;
13296 }
13297
13298 ret = drm_atomic_helper_prepare_planes(dev, state);
13299 if (ret)
13300 return ret;
13301
13302 drm_atomic_helper_swap_state(dev, state);
13303
13304 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13306
13307 if (!needs_modeset(crtc->state))
13308 continue;
13309
13310 any_ms = true;
13311 intel_pre_plane_update(intel_crtc);
13312
13313 if (crtc_state->active) {
13314 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13315 dev_priv->display.crtc_disable(crtc);
13316 intel_crtc->active = false;
13317 intel_disable_shared_dpll(intel_crtc);
13318 }
13319 }
13320
13321 /* Only after disabling all output pipelines that will be changed can we
13322 * update the the output configuration. */
13323 intel_modeset_update_crtc_state(state);
13324
13325 if (any_ms) {
13326 intel_shared_dpll_commit(state);
13327
13328 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13329 modeset_update_crtc_power_domains(state);
13330 }
13331
13332 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13333 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13335 bool modeset = needs_modeset(crtc->state);
13336 bool update_pipe = !modeset &&
13337 to_intel_crtc_state(crtc->state)->update_pipe;
13338 unsigned long put_domains = 0;
13339
13340 if (modeset && crtc->state->active) {
13341 update_scanline_offset(to_intel_crtc(crtc));
13342 dev_priv->display.crtc_enable(crtc);
13343 }
13344
13345 if (update_pipe) {
13346 put_domains = modeset_get_crtc_power_domains(crtc);
13347
13348 /* make sure intel_modeset_check_state runs */
13349 any_ms = true;
13350 }
13351
13352 if (!modeset)
13353 intel_pre_plane_update(intel_crtc);
13354
13355 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13356
13357 if (put_domains)
13358 modeset_put_power_domains(dev_priv, put_domains);
13359
13360 intel_post_plane_update(intel_crtc);
13361 }
13362
13363 /* FIXME: add subpixel order */
13364
13365 drm_atomic_helper_wait_for_vblanks(dev, state);
13366 drm_atomic_helper_cleanup_planes(dev, state);
13367
13368 if (any_ms)
13369 intel_modeset_check_state(dev, state);
13370
13371 drm_atomic_state_free(state);
13372
13373 return 0;
13374}
13375
13376void intel_crtc_restore_mode(struct drm_crtc *crtc)
13377{
13378 struct drm_device *dev = crtc->dev;
13379 struct drm_atomic_state *state;
13380 struct drm_crtc_state *crtc_state;
13381 int ret;
13382
13383 state = drm_atomic_state_alloc(dev);
13384 if (!state) {
13385 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13386 crtc->base.id);
13387 return;
13388 }
13389
13390 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13391
13392retry:
13393 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13394 ret = PTR_ERR_OR_ZERO(crtc_state);
13395 if (!ret) {
13396 if (!crtc_state->active)
13397 goto out;
13398
13399 crtc_state->mode_changed = true;
13400 ret = drm_atomic_commit(state);
13401 }
13402
13403 if (ret == -EDEADLK) {
13404 drm_atomic_state_clear(state);
13405 drm_modeset_backoff(state->acquire_ctx);
13406 goto retry;
13407 }
13408
13409 if (ret)
13410out:
13411 drm_atomic_state_free(state);
13412}
13413
13414#undef for_each_intel_crtc_masked
13415
13416static const struct drm_crtc_funcs intel_crtc_funcs = {
13417 .gamma_set = intel_crtc_gamma_set,
13418 .set_config = drm_atomic_helper_set_config,
13419 .destroy = intel_crtc_destroy,
13420 .page_flip = intel_crtc_page_flip,
13421 .atomic_duplicate_state = intel_crtc_duplicate_state,
13422 .atomic_destroy_state = intel_crtc_destroy_state,
13423};
13424
13425static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13426 struct intel_shared_dpll *pll,
13427 struct intel_dpll_hw_state *hw_state)
13428{
13429 uint32_t val;
13430
13431 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13432 return false;
13433
13434 val = I915_READ(PCH_DPLL(pll->id));
13435 hw_state->dpll = val;
13436 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13437 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13438
13439 return val & DPLL_VCO_ENABLE;
13440}
13441
13442static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13443 struct intel_shared_dpll *pll)
13444{
13445 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13446 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13447}
13448
13449static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13450 struct intel_shared_dpll *pll)
13451{
13452 /* PCH refclock must be enabled first */
13453 ibx_assert_pch_refclk_enabled(dev_priv);
13454
13455 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13456
13457 /* Wait for the clocks to stabilize. */
13458 POSTING_READ(PCH_DPLL(pll->id));
13459 udelay(150);
13460
13461 /* The pixel multiplier can only be updated once the
13462 * DPLL is enabled and the clocks are stable.
13463 *
13464 * So write it again.
13465 */
13466 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13467 POSTING_READ(PCH_DPLL(pll->id));
13468 udelay(200);
13469}
13470
13471static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13472 struct intel_shared_dpll *pll)
13473{
13474 struct drm_device *dev = dev_priv->dev;
13475 struct intel_crtc *crtc;
13476
13477 /* Make sure no transcoder isn't still depending on us. */
13478 for_each_intel_crtc(dev, crtc) {
13479 if (intel_crtc_to_shared_dpll(crtc) == pll)
13480 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13481 }
13482
13483 I915_WRITE(PCH_DPLL(pll->id), 0);
13484 POSTING_READ(PCH_DPLL(pll->id));
13485 udelay(200);
13486}
13487
13488static const char *ibx_pch_dpll_names[] = {
13489 "PCH DPLL A",
13490 "PCH DPLL B",
13491};
13492
13493static void ibx_pch_dpll_init(struct drm_device *dev)
13494{
13495 struct drm_i915_private *dev_priv = dev->dev_private;
13496 int i;
13497
13498 dev_priv->num_shared_dpll = 2;
13499
13500 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13501 dev_priv->shared_dplls[i].id = i;
13502 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13503 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13504 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13505 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13506 dev_priv->shared_dplls[i].get_hw_state =
13507 ibx_pch_dpll_get_hw_state;
13508 }
13509}
13510
13511static void intel_shared_dpll_init(struct drm_device *dev)
13512{
13513 struct drm_i915_private *dev_priv = dev->dev_private;
13514
13515 if (HAS_DDI(dev))
13516 intel_ddi_pll_init(dev);
13517 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13518 ibx_pch_dpll_init(dev);
13519 else
13520 dev_priv->num_shared_dpll = 0;
13521
13522 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13523}
13524
13525/**
13526 * intel_prepare_plane_fb - Prepare fb for usage on plane
13527 * @plane: drm plane to prepare for
13528 * @fb: framebuffer to prepare for presentation
13529 *
13530 * Prepares a framebuffer for usage on a display plane. Generally this
13531 * involves pinning the underlying object and updating the frontbuffer tracking
13532 * bits. Some older platforms need special physical address handling for
13533 * cursor planes.
13534 *
13535 * Returns 0 on success, negative error code on failure.
13536 */
13537int
13538intel_prepare_plane_fb(struct drm_plane *plane,
13539 const struct drm_plane_state *new_state)
13540{
13541 struct drm_device *dev = plane->dev;
13542 struct drm_framebuffer *fb = new_state->fb;
13543 struct intel_plane *intel_plane = to_intel_plane(plane);
13544 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13545 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13546 int ret = 0;
13547
13548 if (!obj)
13549 return 0;
13550
13551 mutex_lock(&dev->struct_mutex);
13552
13553 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13554 INTEL_INFO(dev)->cursor_needs_physical) {
13555 int align = IS_I830(dev) ? 16 * 1024 : 256;
13556 ret = i915_gem_object_attach_phys(obj, align);
13557 if (ret)
13558 DRM_DEBUG_KMS("failed to attach phys object\n");
13559 } else {
13560 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13561 }
13562
13563 if (ret == 0)
13564 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13565
13566 mutex_unlock(&dev->struct_mutex);
13567
13568 return ret;
13569}
13570
13571/**
13572 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13573 * @plane: drm plane to clean up for
13574 * @fb: old framebuffer that was on plane
13575 *
13576 * Cleans up a framebuffer that has just been removed from a plane.
13577 */
13578void
13579intel_cleanup_plane_fb(struct drm_plane *plane,
13580 const struct drm_plane_state *old_state)
13581{
13582 struct drm_device *dev = plane->dev;
13583 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13584
13585 if (!obj)
13586 return;
13587
13588 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13589 !INTEL_INFO(dev)->cursor_needs_physical) {
13590 mutex_lock(&dev->struct_mutex);
13591 intel_unpin_fb_obj(old_state->fb, old_state);
13592 mutex_unlock(&dev->struct_mutex);
13593 }
13594}
13595
13596int
13597skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13598{
13599 int max_scale;
13600 struct drm_device *dev;
13601 struct drm_i915_private *dev_priv __unused;
13602 int crtc_clock, cdclk;
13603
13604 if (!intel_crtc || !crtc_state)
13605 return DRM_PLANE_HELPER_NO_SCALING;
13606
13607 dev = intel_crtc->base.dev;
13608 dev_priv = dev->dev_private;
13609 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13610 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13611
13612 if (!crtc_clock || !cdclk)
13613 return DRM_PLANE_HELPER_NO_SCALING;
13614
13615 /*
13616 * skl max scale is lower of:
13617 * close to 3 but not 3, -1 is for that purpose
13618 * or
13619 * cdclk/crtc_clock
13620 */
13621 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13622
13623 return max_scale;
13624}
13625
13626static int
13627intel_check_primary_plane(struct drm_plane *plane,
13628 struct intel_crtc_state *crtc_state,
13629 struct intel_plane_state *state)
13630{
13631 struct drm_crtc *crtc = state->base.crtc;
13632 struct drm_framebuffer *fb = state->base.fb;
13633 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13634 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13635 bool can_position = false;
13636
13637 if (INTEL_INFO(plane->dev)->gen >= 9) {
13638 /* use scaler when colorkey is not required */
13639 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13640 min_scale = 1;
13641 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13642 }
13643 can_position = true;
13644 }
13645
13646 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13647 &state->dst, &state->clip,
13648 min_scale, max_scale,
13649 can_position, true,
13650 &state->visible);
13651}
13652
13653static void
13654intel_commit_primary_plane(struct drm_plane *plane,
13655 struct intel_plane_state *state)
13656{
13657 struct drm_crtc *crtc = state->base.crtc;
13658 struct drm_framebuffer *fb = state->base.fb;
13659 struct drm_device *dev = plane->dev;
13660 struct drm_i915_private *dev_priv = dev->dev_private;
13661 struct intel_crtc *intel_crtc __unused;
13662 struct drm_rect *src = &state->src;
13663
13664 crtc = crtc ? crtc : plane->crtc;
13665 intel_crtc = to_intel_crtc(crtc);
13666
13667 plane->fb = fb;
13668 crtc->x = src->x1 >> 16;
13669 crtc->y = src->y1 >> 16;
13670
13671 if (!crtc->state->active)
13672 return;
13673
13674 dev_priv->display.update_primary_plane(crtc, fb,
13675 state->src.x1 >> 16,
13676 state->src.y1 >> 16);
13677}
13678
13679static void
13680intel_disable_primary_plane(struct drm_plane *plane,
13681 struct drm_crtc *crtc)
13682{
13683 struct drm_device *dev = plane->dev;
13684 struct drm_i915_private *dev_priv = dev->dev_private;
13685
13686 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13687}
13688
13689static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13690 struct drm_crtc_state *old_crtc_state)
13691{
13692 struct drm_device *dev = crtc->dev;
13693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13694 struct intel_crtc_state *old_intel_state =
13695 to_intel_crtc_state(old_crtc_state);
13696 bool modeset = needs_modeset(crtc->state);
13697
13698 if (intel_crtc->atomic.update_wm_pre)
13699 intel_update_watermarks(crtc);
13700
13701 /* Perform vblank evasion around commit operation */
13702 if (crtc->state->active)
13703 intel_pipe_update_start(intel_crtc);
13704
13705 if (modeset)
13706 return;
13707
13708 if (to_intel_crtc_state(crtc->state)->update_pipe)
13709 intel_update_pipe_config(intel_crtc, old_intel_state);
13710 else if (INTEL_INFO(dev)->gen >= 9)
13711 skl_detach_scalers(intel_crtc);
13712}
13713
13714static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13715 struct drm_crtc_state *old_crtc_state)
13716{
13717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13718
13719 if (crtc->state->active)
13720 intel_pipe_update_end(intel_crtc);
13721}
13722
13723/**
13724 * intel_plane_destroy - destroy a plane
13725 * @plane: plane to destroy
13726 *
13727 * Common destruction function for all types of planes (primary, cursor,
13728 * sprite).
13729 */
13730void intel_plane_destroy(struct drm_plane *plane)
13731{
13732 struct intel_plane *intel_plane = to_intel_plane(plane);
13733 drm_plane_cleanup(plane);
13734 kfree(intel_plane);
13735}
13736
13737const struct drm_plane_funcs intel_plane_funcs = {
13738 .update_plane = drm_atomic_helper_update_plane,
13739 .disable_plane = drm_atomic_helper_disable_plane,
13740 .destroy = intel_plane_destroy,
13741 .set_property = drm_atomic_helper_plane_set_property,
13742 .atomic_get_property = intel_plane_atomic_get_property,
13743 .atomic_set_property = intel_plane_atomic_set_property,
13744 .atomic_duplicate_state = intel_plane_duplicate_state,
13745 .atomic_destroy_state = intel_plane_destroy_state,
13746
13747};
13748
13749static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13750 int pipe)
13751{
13752 struct intel_plane *primary;
13753 struct intel_plane_state *state;
13754 const uint32_t *intel_primary_formats;
13755 unsigned int num_formats;
13756
13757 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13758 if (primary == NULL)
13759 return NULL;
13760
13761 state = intel_create_plane_state(&primary->base);
13762 if (!state) {
13763 kfree(primary);
13764 return NULL;
13765 }
13766 primary->base.state = &state->base;
13767
13768 primary->can_scale = false;
13769 primary->max_downscale = 1;
13770 if (INTEL_INFO(dev)->gen >= 9) {
13771 primary->can_scale = true;
13772 state->scaler_id = -1;
13773 }
13774 primary->pipe = pipe;
13775 primary->plane = pipe;
13776 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13777 primary->check_plane = intel_check_primary_plane;
13778 primary->commit_plane = intel_commit_primary_plane;
13779 primary->disable_plane = intel_disable_primary_plane;
13780 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13781 primary->plane = !pipe;
13782
13783 if (INTEL_INFO(dev)->gen >= 9) {
13784 intel_primary_formats = skl_primary_formats;
13785 num_formats = ARRAY_SIZE(skl_primary_formats);
13786 } else if (INTEL_INFO(dev)->gen >= 4) {
13787 intel_primary_formats = i965_primary_formats;
13788 num_formats = ARRAY_SIZE(i965_primary_formats);
13789 } else {
13790 intel_primary_formats = i8xx_primary_formats;
13791 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13792 }
13793
13794 drm_universal_plane_init(dev, &primary->base, 0,
13795 &intel_plane_funcs,
13796 intel_primary_formats, num_formats,
13797 DRM_PLANE_TYPE_PRIMARY);
13798
13799 if (INTEL_INFO(dev)->gen >= 4)
13800 intel_create_rotation_property(dev, primary);
13801
13802 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13803
13804 return &primary->base;
13805}
13806
13807void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13808{
13809 if (!dev->mode_config.rotation_property) {
13810 unsigned long flags = BIT(DRM_ROTATE_0) |
13811 BIT(DRM_ROTATE_180);
13812
13813 if (INTEL_INFO(dev)->gen >= 9)
13814 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13815
13816 dev->mode_config.rotation_property =
13817 drm_mode_create_rotation_property(dev, flags);
13818 }
13819 if (dev->mode_config.rotation_property)
13820 drm_object_attach_property(&plane->base.base,
13821 dev->mode_config.rotation_property,
13822 plane->base.state->rotation);
13823}
13824
13825static int
13826intel_check_cursor_plane(struct drm_plane *plane,
13827 struct intel_crtc_state *crtc_state,
13828 struct intel_plane_state *state)
13829{
13830 struct drm_crtc *crtc = crtc_state->base.crtc;
13831 struct drm_framebuffer *fb = state->base.fb;
13832 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13833 enum i915_pipe pipe = to_intel_plane(plane)->pipe;
13834 unsigned stride;
13835 int ret;
13836
13837 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13838 &state->dst, &state->clip,
13839 DRM_PLANE_HELPER_NO_SCALING,
13840 DRM_PLANE_HELPER_NO_SCALING,
13841 true, true, &state->visible);
13842 if (ret)
13843 return ret;
13844
13845 /* if we want to turn off the cursor ignore width and height */
13846 if (!obj)
13847 return 0;
13848
13849 /* Check for which cursor types we support */
13850 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13851 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13852 state->base.crtc_w, state->base.crtc_h);
13853 return -EINVAL;
13854 }
13855
13856 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13857 if (obj->base.size < stride * state->base.crtc_h) {
13858 DRM_DEBUG_KMS("buffer is too small\n");
13859 return -ENOMEM;
13860 }
13861
13862 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13863 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13864 return -EINVAL;
13865 }
13866
13867 /*
13868 * There's something wrong with the cursor on CHV pipe C.
13869 * If it straddles the left edge of the screen then
13870 * moving it away from the edge or disabling it often
13871 * results in a pipe underrun, and often that can lead to
13872 * dead pipe (constant underrun reported, and it scans
13873 * out just a solid color). To recover from that, the
13874 * display power well must be turned off and on again.
13875 * Refuse the put the cursor into that compromised position.
13876 */
13877 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
13878 state->visible && state->base.crtc_x < 0) {
13879 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13880 return -EINVAL;
13881 }
13882
13883 return 0;
13884}
13885
13886static void
13887intel_disable_cursor_plane(struct drm_plane *plane,
13888 struct drm_crtc *crtc)
13889{
13890 intel_crtc_update_cursor(crtc, false);
13891}
13892
13893static void
13894intel_commit_cursor_plane(struct drm_plane *plane,
13895 struct intel_plane_state *state)
13896{
13897 struct drm_crtc *crtc = state->base.crtc;
13898 struct drm_device *dev = plane->dev;
13899 struct intel_crtc *intel_crtc;
13900 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13901 uint32_t addr;
13902
13903 crtc = crtc ? crtc : plane->crtc;
13904 intel_crtc = to_intel_crtc(crtc);
13905
13906 if (!obj)
13907 addr = 0;
13908 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13909 addr = i915_gem_obj_ggtt_offset(obj);
13910 else
13911 addr = obj->phys_handle->busaddr;
13912
13913 intel_crtc->cursor_addr = addr;
13914
13915 if (crtc->state->active)
13916 intel_crtc_update_cursor(crtc, state->visible);
13917}
13918
13919static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13920 int pipe)
13921{
13922 struct intel_plane *cursor;
13923 struct intel_plane_state *state;
13924
13925 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13926 if (cursor == NULL)
13927 return NULL;
13928
13929 state = intel_create_plane_state(&cursor->base);
13930 if (!state) {
13931 kfree(cursor);
13932 return NULL;
13933 }
13934 cursor->base.state = &state->base;
13935
13936 cursor->can_scale = false;
13937 cursor->max_downscale = 1;
13938 cursor->pipe = pipe;
13939 cursor->plane = pipe;
13940 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13941 cursor->check_plane = intel_check_cursor_plane;
13942 cursor->commit_plane = intel_commit_cursor_plane;
13943 cursor->disable_plane = intel_disable_cursor_plane;
13944
13945 drm_universal_plane_init(dev, &cursor->base, 0,
13946 &intel_plane_funcs,
13947 intel_cursor_formats,
13948 ARRAY_SIZE(intel_cursor_formats),
13949 DRM_PLANE_TYPE_CURSOR);
13950
13951 if (INTEL_INFO(dev)->gen >= 4) {
13952 if (!dev->mode_config.rotation_property)
13953 dev->mode_config.rotation_property =
13954 drm_mode_create_rotation_property(dev,
13955 BIT(DRM_ROTATE_0) |
13956 BIT(DRM_ROTATE_180));
13957 if (dev->mode_config.rotation_property)
13958 drm_object_attach_property(&cursor->base.base,
13959 dev->mode_config.rotation_property,
13960 state->base.rotation);
13961 }
13962
13963 if (INTEL_INFO(dev)->gen >=9)
13964 state->scaler_id = -1;
13965
13966 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13967
13968 return &cursor->base;
13969}
13970
13971static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13972 struct intel_crtc_state *crtc_state)
13973{
13974 int i;
13975 struct intel_scaler *intel_scaler;
13976 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13977
13978 for (i = 0; i < intel_crtc->num_scalers; i++) {
13979 intel_scaler = &scaler_state->scalers[i];
13980 intel_scaler->in_use = 0;
13981 intel_scaler->mode = PS_SCALER_MODE_DYN;
13982 }
13983
13984 scaler_state->scaler_id = -1;
13985}
13986
13987static void intel_crtc_init(struct drm_device *dev, int pipe)
13988{
13989 struct drm_i915_private *dev_priv = dev->dev_private;
13990 struct intel_crtc *intel_crtc;
13991 struct intel_crtc_state *crtc_state = NULL;
13992 struct drm_plane *primary = NULL;
13993 struct drm_plane *cursor = NULL;
13994 int i, ret;
13995
13996 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13997 if (intel_crtc == NULL)
13998 return;
13999
14000 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14001 if (!crtc_state)
14002 goto fail;
14003 intel_crtc->config = crtc_state;
14004 intel_crtc->base.state = &crtc_state->base;
14005 crtc_state->base.crtc = &intel_crtc->base;
14006
14007 /* initialize shared scalers */
14008 if (INTEL_INFO(dev)->gen >= 9) {
14009 if (pipe == PIPE_C)
14010 intel_crtc->num_scalers = 1;
14011 else
14012 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14013
14014 skl_init_scalers(dev, intel_crtc, crtc_state);
14015 }
14016
14017 primary = intel_primary_plane_create(dev, pipe);
14018 if (!primary)
14019 goto fail;
14020
14021 cursor = intel_cursor_plane_create(dev, pipe);
14022 if (!cursor)
14023 goto fail;
14024
14025 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14026 cursor, &intel_crtc_funcs);
14027 if (ret)
14028 goto fail;
14029
14030 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14031 for (i = 0; i < 256; i++) {
14032 intel_crtc->lut_r[i] = i;
14033 intel_crtc->lut_g[i] = i;
14034 intel_crtc->lut_b[i] = i;
14035 }
14036
14037 /*
14038 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14039 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14040 */
14041 intel_crtc->pipe = pipe;
14042 intel_crtc->plane = pipe;
14043 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14044 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14045 intel_crtc->plane = !pipe;
14046 }
14047
14048 intel_crtc->cursor_base = ~0;
14049 intel_crtc->cursor_cntl = ~0;
14050 intel_crtc->cursor_size = ~0;
14051
14052 intel_crtc->wm.cxsr_allowed = true;
14053
14054 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14055 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14056 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14057 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14058
14059 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14060
14061 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14062 return;
14063
14064fail:
14065 if (primary)
14066 drm_plane_cleanup(primary);
14067 if (cursor)
14068 drm_plane_cleanup(cursor);
14069 kfree(crtc_state);
14070 kfree(intel_crtc);
14071}
14072
14073enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14074{
14075 struct drm_encoder *encoder = connector->base.encoder;
14076 struct drm_device *dev = connector->base.dev;
14077
14078 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14079
14080 if (!encoder || WARN_ON(!encoder->crtc))
14081 return INVALID_PIPE;
14082
14083 return to_intel_crtc(encoder->crtc)->pipe;
14084}
14085
14086int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14087 struct drm_file *file)
14088{
14089 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14090 struct drm_crtc *drmmode_crtc;
14091 struct intel_crtc *crtc;
14092
14093 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14094
14095 if (!drmmode_crtc) {
14096 DRM_ERROR("no such CRTC id\n");
14097 return -ENOENT;
14098 }
14099
14100 crtc = to_intel_crtc(drmmode_crtc);
14101 pipe_from_crtc_id->pipe = crtc->pipe;
14102
14103 return 0;
14104}
14105
14106static int intel_encoder_clones(struct intel_encoder *encoder)
14107{
14108 struct drm_device *dev = encoder->base.dev;
14109 struct intel_encoder *source_encoder;
14110 int index_mask = 0;
14111 int entry = 0;
14112
14113 for_each_intel_encoder(dev, source_encoder) {
14114 if (encoders_cloneable(encoder, source_encoder))
14115 index_mask |= (1 << entry);
14116
14117 entry++;
14118 }
14119
14120 return index_mask;
14121}
14122
14123static bool has_edp_a(struct drm_device *dev)
14124{
14125 struct drm_i915_private *dev_priv = dev->dev_private;
14126
14127 if (!IS_MOBILE(dev))
14128 return false;
14129
14130 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14131 return false;
14132
14133 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14134 return false;
14135
14136 return true;
14137}
14138
14139static bool intel_crt_present(struct drm_device *dev)
14140{
14141 struct drm_i915_private *dev_priv = dev->dev_private;
14142
14143 if (INTEL_INFO(dev)->gen >= 9)
14144 return false;
14145
14146 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14147 return false;
14148
14149 if (IS_CHERRYVIEW(dev))
14150 return false;
14151
14152 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14153 return false;
14154
14155 return true;
14156}
14157
14158static void intel_setup_outputs(struct drm_device *dev)
14159{
14160 struct drm_i915_private *dev_priv = dev->dev_private;
14161 struct intel_encoder *encoder;
14162 bool dpd_is_edp = false;
14163
14164 intel_lvds_init(dev);
14165
14166 if (intel_crt_present(dev))
14167 intel_crt_init(dev);
14168
14169 if (IS_BROXTON(dev)) {
14170 /*
14171 * FIXME: Broxton doesn't support port detection via the
14172 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14173 * detect the ports.
14174 */
14175 intel_ddi_init(dev, PORT_A);
14176 intel_ddi_init(dev, PORT_B);
14177 intel_ddi_init(dev, PORT_C);
14178 } else if (HAS_DDI(dev)) {
14179 int found;
14180
14181 /*
14182 * Haswell uses DDI functions to detect digital outputs.
14183 * On SKL pre-D0 the strap isn't connected, so we assume
14184 * it's there.
14185 */
14186 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14187 /* WaIgnoreDDIAStrap: skl */
14188 if (found || (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)))
14189 intel_ddi_init(dev, PORT_A);
14190
14191 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14192 * register */
14193 found = I915_READ(SFUSE_STRAP);
14194
14195 if (found & SFUSE_STRAP_DDIB_DETECTED)
14196 intel_ddi_init(dev, PORT_B);
14197 if (found & SFUSE_STRAP_DDIC_DETECTED)
14198 intel_ddi_init(dev, PORT_C);
14199 if (found & SFUSE_STRAP_DDID_DETECTED)
14200 intel_ddi_init(dev, PORT_D);
14201 /*
14202 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14203 */
14204 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14205 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14206 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14207 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14208 intel_ddi_init(dev, PORT_E);
14209
14210 } else if (HAS_PCH_SPLIT(dev)) {
14211 int found;
14212 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14213
14214 if (has_edp_a(dev))
14215 intel_dp_init(dev, DP_A, PORT_A);
14216
14217 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14218 /* PCH SDVOB multiplex with HDMIB */
14219 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14220 if (!found)
14221 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14222 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14223 intel_dp_init(dev, PCH_DP_B, PORT_B);
14224 }
14225
14226 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14227 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14228
14229 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14230 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14231
14232 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14233 intel_dp_init(dev, PCH_DP_C, PORT_C);
14234
14235 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14236 intel_dp_init(dev, PCH_DP_D, PORT_D);
14237 } else if (IS_VALLEYVIEW(dev)) {
14238 bool has_edp, has_port;
14239
14240 /*
14241 * The DP_DETECTED bit is the latched state of the DDC
14242 * SDA pin at boot. However since eDP doesn't require DDC
14243 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14244 * eDP ports may have been muxed to an alternate function.
14245 * Thus we can't rely on the DP_DETECTED bit alone to detect
14246 * eDP ports. Consult the VBT as well as DP_DETECTED to
14247 * detect eDP ports.
14248 *
14249 * Sadly the straps seem to be missing sometimes even for HDMI
14250 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14251 * and VBT for the presence of the port. Additionally we can't
14252 * trust the port type the VBT declares as we've seen at least
14253 * HDMI ports that the VBT claim are DP or eDP.
14254 */
14255 has_edp = intel_dp_is_edp(dev, PORT_B);
14256 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14257 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14258 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14259 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14260 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14261
14262 has_edp = intel_dp_is_edp(dev, PORT_C);
14263 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14264 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14265 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14266 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14267 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14268
14269 if (IS_CHERRYVIEW(dev)) {
14270 /*
14271 * eDP not supported on port D,
14272 * so no need to worry about it
14273 */
14274 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14275 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14276 intel_dp_init(dev, CHV_DP_D, PORT_D);
14277 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14278 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14279 }
14280
14281 intel_dsi_init(dev);
14282 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14283 bool found = false;
14284
14285 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14286 DRM_DEBUG_KMS("probing SDVOB\n");
14287 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14288 if (!found && IS_G4X(dev)) {
14289 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14290 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14291 }
14292
14293 if (!found && IS_G4X(dev))
14294 intel_dp_init(dev, DP_B, PORT_B);
14295 }
14296
14297 /* Before G4X SDVOC doesn't have its own detect register */
14298
14299 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14300 DRM_DEBUG_KMS("probing SDVOC\n");
14301 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14302 }
14303
14304 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14305
14306 if (IS_G4X(dev)) {
14307 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14308 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14309 }
14310 if (IS_G4X(dev))
14311 intel_dp_init(dev, DP_C, PORT_C);
14312 }
14313
14314 if (IS_G4X(dev) &&
14315 (I915_READ(DP_D) & DP_DETECTED))
14316 intel_dp_init(dev, DP_D, PORT_D);
14317 } else if (IS_GEN2(dev))
14318 intel_dvo_init(dev);
14319
14320 if (SUPPORTS_TV(dev))
14321 intel_tv_init(dev);
14322
14323 intel_psr_init(dev);
14324
14325 for_each_intel_encoder(dev, encoder) {
14326 encoder->base.possible_crtcs = encoder->crtc_mask;
14327 encoder->base.possible_clones =
14328 intel_encoder_clones(encoder);
14329 }
14330
14331 intel_init_pch_refclk(dev);
14332
14333 drm_helper_move_panel_connectors_to_head(dev);
14334}
14335
14336static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14337{
14338 struct drm_device *dev = fb->dev;
14339 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14340
14341 drm_framebuffer_cleanup(fb);
14342 mutex_lock(&dev->struct_mutex);
14343 WARN_ON(!intel_fb->obj->framebuffer_references--);
14344 drm_gem_object_unreference(&intel_fb->obj->base);
14345 mutex_unlock(&dev->struct_mutex);
14346 kfree(intel_fb);
14347}
14348
14349static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14350 struct drm_file *file,
14351 unsigned int *handle)
14352{
14353 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14354 struct drm_i915_gem_object *obj = intel_fb->obj;
14355
14356 if (obj->userptr.mm) {
14357 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14358 return -EINVAL;
14359 }
14360
14361 return drm_gem_handle_create(file, &obj->base, handle);
14362}
14363
14364static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14365 struct drm_file *file,
14366 unsigned flags, unsigned color,
14367 struct drm_clip_rect *clips,
14368 unsigned num_clips)
14369{
14370 struct drm_device *dev = fb->dev;
14371 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14372 struct drm_i915_gem_object *obj = intel_fb->obj;
14373
14374 mutex_lock(&dev->struct_mutex);
14375 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14376 mutex_unlock(&dev->struct_mutex);
14377
14378 return 0;
14379}
14380
14381static const struct drm_framebuffer_funcs intel_fb_funcs = {
14382 .destroy = intel_user_framebuffer_destroy,
14383 .create_handle = intel_user_framebuffer_create_handle,
14384 .dirty = intel_user_framebuffer_dirty,
14385};
14386
14387static
14388u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14389 uint32_t pixel_format)
14390{
14391 u32 gen = INTEL_INFO(dev)->gen;
14392
14393 if (gen >= 9) {
14394 /* "The stride in bytes must not exceed the of the size of 8K
14395 * pixels and 32K bytes."
14396 */
14397 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14398 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14399 return 32*1024;
14400 } else if (gen >= 4) {
14401 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14402 return 16*1024;
14403 else
14404 return 32*1024;
14405 } else if (gen >= 3) {
14406 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14407 return 8*1024;
14408 else
14409 return 16*1024;
14410 } else {
14411 /* XXX DSPC is limited to 4k tiled */
14412 return 8*1024;
14413 }
14414}
14415
14416static int intel_framebuffer_init(struct drm_device *dev,
14417 struct intel_framebuffer *intel_fb,
14418 struct drm_mode_fb_cmd2 *mode_cmd,
14419 struct drm_i915_gem_object *obj)
14420{
14421 unsigned int aligned_height;
14422 int ret;
14423 u32 pitch_limit, stride_alignment;
14424
14425 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14426
14427 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14428 /* Enforce that fb modifier and tiling mode match, but only for
14429 * X-tiled. This is needed for FBC. */
14430 if (!!(obj->tiling_mode == I915_TILING_X) !=
14431 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14432 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14433 return -EINVAL;
14434 }
14435 } else {
14436 if (obj->tiling_mode == I915_TILING_X)
14437 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14438 else if (obj->tiling_mode == I915_TILING_Y) {
14439 DRM_DEBUG("No Y tiling for legacy addfb\n");
14440 return -EINVAL;
14441 }
14442 }
14443
14444 /* Passed in modifier sanity checking. */
14445 switch (mode_cmd->modifier[0]) {
14446 case I915_FORMAT_MOD_Y_TILED:
14447 case I915_FORMAT_MOD_Yf_TILED:
14448 if (INTEL_INFO(dev)->gen < 9) {
14449 DRM_DEBUG("Unsupported tiling 0x%"PRIx64"!\n",
14450 mode_cmd->modifier[0]);
14451 return -EINVAL;
14452 }
14453 case DRM_FORMAT_MOD_NONE:
14454 case I915_FORMAT_MOD_X_TILED:
14455 break;
14456 default:
14457 DRM_DEBUG("Unsupported fb modifier 0x%"PRIx64"!\n",
14458 mode_cmd->modifier[0]);
14459 return -EINVAL;
14460 }
14461
14462 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14463 mode_cmd->pixel_format);
14464 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14465 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14466 mode_cmd->pitches[0], stride_alignment);
14467 return -EINVAL;
14468 }
14469
14470 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14471 mode_cmd->pixel_format);
14472 if (mode_cmd->pitches[0] > pitch_limit) {
14473 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14474 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14475 "tiled" : "linear",
14476 mode_cmd->pitches[0], pitch_limit);
14477 return -EINVAL;
14478 }
14479
14480 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14481 mode_cmd->pitches[0] != obj->stride) {
14482 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14483 mode_cmd->pitches[0], obj->stride);
14484 return -EINVAL;
14485 }
14486
14487 /* Reject formats not supported by any plane early. */
14488 switch (mode_cmd->pixel_format) {
14489 case DRM_FORMAT_C8:
14490 case DRM_FORMAT_RGB565:
14491 case DRM_FORMAT_XRGB8888:
14492 case DRM_FORMAT_ARGB8888:
14493 break;
14494 case DRM_FORMAT_XRGB1555:
14495 if (INTEL_INFO(dev)->gen > 3) {
14496 DRM_DEBUG("unsupported pixel format: %s\n",
14497 drm_get_format_name(mode_cmd->pixel_format));
14498 return -EINVAL;
14499 }
14500 break;
14501 case DRM_FORMAT_ABGR8888:
14502 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14503 DRM_DEBUG("unsupported pixel format: %s\n",
14504 drm_get_format_name(mode_cmd->pixel_format));
14505 return -EINVAL;
14506 }
14507 break;
14508 case DRM_FORMAT_XBGR8888:
14509 case DRM_FORMAT_XRGB2101010:
14510 case DRM_FORMAT_XBGR2101010:
14511 if (INTEL_INFO(dev)->gen < 4) {
14512 DRM_DEBUG("unsupported pixel format: %s\n",
14513 drm_get_format_name(mode_cmd->pixel_format));
14514 return -EINVAL;
14515 }
14516 break;
14517 case DRM_FORMAT_ABGR2101010:
14518 if (!IS_VALLEYVIEW(dev)) {
14519 DRM_DEBUG("unsupported pixel format: %s\n",
14520 drm_get_format_name(mode_cmd->pixel_format));
14521 return -EINVAL;
14522 }
14523 break;
14524 case DRM_FORMAT_YUYV:
14525 case DRM_FORMAT_UYVY:
14526 case DRM_FORMAT_YVYU:
14527 case DRM_FORMAT_VYUY:
14528 if (INTEL_INFO(dev)->gen < 5) {
14529 DRM_DEBUG("unsupported pixel format: %s\n",
14530 drm_get_format_name(mode_cmd->pixel_format));
14531 return -EINVAL;
14532 }
14533 break;
14534 default:
14535 DRM_DEBUG("unsupported pixel format: %s\n",
14536 drm_get_format_name(mode_cmd->pixel_format));
14537 return -EINVAL;
14538 }
14539
14540 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14541 if (mode_cmd->offsets[0] != 0)
14542 return -EINVAL;
14543
14544 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14545 mode_cmd->pixel_format,
14546 mode_cmd->modifier[0]);
14547 /* FIXME drm helper for size checks (especially planar formats)? */
14548 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14549 return -EINVAL;
14550
14551 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14552 intel_fb->obj = obj;
14553 intel_fb->obj->framebuffer_references++;
14554
14555 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14556 if (ret) {
14557 DRM_ERROR("framebuffer init failed %d\n", ret);
14558 return ret;
14559 }
14560
14561 return 0;
14562}
14563
14564static struct drm_framebuffer *
14565intel_user_framebuffer_create(struct drm_device *dev,
14566 struct drm_file *filp,
14567 struct drm_mode_fb_cmd2 *user_mode_cmd)
14568{
14569 struct drm_gem_object *gobj;
14570 struct drm_i915_gem_object *obj;
14571 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14572
14573 gobj = drm_gem_object_lookup(dev, filp, mode_cmd.handles[0]);
14574 if (gobj == NULL)
14575 return ERR_PTR(-ENOENT);
14576 obj = to_intel_bo(gobj);
14577
14578 return intel_framebuffer_create(dev, &mode_cmd, obj);
14579}
14580
14581#ifndef CONFIG_DRM_FBDEV_EMULATION
14582static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14583{
14584}
14585#endif
14586
14587static const struct drm_mode_config_funcs intel_mode_funcs = {
14588 .fb_create = intel_user_framebuffer_create,
14589 .output_poll_changed = intel_fbdev_output_poll_changed,
14590 .atomic_check = intel_atomic_check,
14591 .atomic_commit = intel_atomic_commit,
14592 .atomic_state_alloc = intel_atomic_state_alloc,
14593 .atomic_state_clear = intel_atomic_state_clear,
14594};
14595
14596/* Set up chip specific display functions */
14597static void intel_init_display(struct drm_device *dev)
14598{
14599 struct drm_i915_private *dev_priv = dev->dev_private;
14600
14601 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14602 dev_priv->display.find_dpll = g4x_find_best_dpll;
14603 else if (IS_CHERRYVIEW(dev))
14604 dev_priv->display.find_dpll = chv_find_best_dpll;
14605 else if (IS_VALLEYVIEW(dev))
14606 dev_priv->display.find_dpll = vlv_find_best_dpll;
14607 else if (IS_PINEVIEW(dev))
14608 dev_priv->display.find_dpll = pnv_find_best_dpll;
14609 else
14610 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14611
14612 if (INTEL_INFO(dev)->gen >= 9) {
14613 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14614 dev_priv->display.get_initial_plane_config =
14615 skylake_get_initial_plane_config;
14616 dev_priv->display.crtc_compute_clock =
14617 haswell_crtc_compute_clock;
14618 dev_priv->display.crtc_enable = haswell_crtc_enable;
14619 dev_priv->display.crtc_disable = haswell_crtc_disable;
14620 dev_priv->display.update_primary_plane =
14621 skylake_update_primary_plane;
14622 } else if (HAS_DDI(dev)) {
14623 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14624 dev_priv->display.get_initial_plane_config =
14625 ironlake_get_initial_plane_config;
14626 dev_priv->display.crtc_compute_clock =
14627 haswell_crtc_compute_clock;
14628 dev_priv->display.crtc_enable = haswell_crtc_enable;
14629 dev_priv->display.crtc_disable = haswell_crtc_disable;
14630 dev_priv->display.update_primary_plane =
14631 ironlake_update_primary_plane;
14632 } else if (HAS_PCH_SPLIT(dev)) {
14633 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14634 dev_priv->display.get_initial_plane_config =
14635 ironlake_get_initial_plane_config;
14636 dev_priv->display.crtc_compute_clock =
14637 ironlake_crtc_compute_clock;
14638 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14639 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14640 dev_priv->display.update_primary_plane =
14641 ironlake_update_primary_plane;
14642 } else if (IS_VALLEYVIEW(dev)) {
14643 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14644 dev_priv->display.get_initial_plane_config =
14645 i9xx_get_initial_plane_config;
14646 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14647 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14648 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14649 dev_priv->display.update_primary_plane =
14650 i9xx_update_primary_plane;
14651 } else {
14652 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14653 dev_priv->display.get_initial_plane_config =
14654 i9xx_get_initial_plane_config;
14655 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14656 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14657 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14658 dev_priv->display.update_primary_plane =
14659 i9xx_update_primary_plane;
14660 }
14661
14662 /* Returns the core display clock speed */
14663 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14664 dev_priv->display.get_display_clock_speed =
14665 skylake_get_display_clock_speed;
14666 else if (IS_BROXTON(dev))
14667 dev_priv->display.get_display_clock_speed =
14668 broxton_get_display_clock_speed;
14669 else if (IS_BROADWELL(dev))
14670 dev_priv->display.get_display_clock_speed =
14671 broadwell_get_display_clock_speed;
14672 else if (IS_HASWELL(dev))
14673 dev_priv->display.get_display_clock_speed =
14674 haswell_get_display_clock_speed;
14675 else if (IS_VALLEYVIEW(dev))
14676 dev_priv->display.get_display_clock_speed =
14677 valleyview_get_display_clock_speed;
14678 else if (IS_GEN5(dev))
14679 dev_priv->display.get_display_clock_speed =
14680 ilk_get_display_clock_speed;
14681 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14682 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14683 dev_priv->display.get_display_clock_speed =
14684 i945_get_display_clock_speed;
14685 else if (IS_GM45(dev))
14686 dev_priv->display.get_display_clock_speed =
14687 gm45_get_display_clock_speed;
14688 else if (IS_CRESTLINE(dev))
14689 dev_priv->display.get_display_clock_speed =
14690 i965gm_get_display_clock_speed;
14691 else if (IS_PINEVIEW(dev))
14692 dev_priv->display.get_display_clock_speed =
14693 pnv_get_display_clock_speed;
14694 else if (IS_G33(dev) || IS_G4X(dev))
14695 dev_priv->display.get_display_clock_speed =
14696 g33_get_display_clock_speed;
14697 else if (IS_I915G(dev))
14698 dev_priv->display.get_display_clock_speed =
14699 i915_get_display_clock_speed;
14700 else if (IS_I945GM(dev) || IS_845G(dev))
14701 dev_priv->display.get_display_clock_speed =
14702 i9xx_misc_get_display_clock_speed;
14703 else if (IS_PINEVIEW(dev))
14704 dev_priv->display.get_display_clock_speed =
14705 pnv_get_display_clock_speed;
14706 else if (IS_I915GM(dev))
14707 dev_priv->display.get_display_clock_speed =
14708 i915gm_get_display_clock_speed;
14709 else if (IS_I865G(dev))
14710 dev_priv->display.get_display_clock_speed =
14711 i865_get_display_clock_speed;
14712 else if (IS_I85X(dev))
14713 dev_priv->display.get_display_clock_speed =
14714 i85x_get_display_clock_speed;
14715 else { /* 830 */
14716 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14717 dev_priv->display.get_display_clock_speed =
14718 i830_get_display_clock_speed;
14719 }
14720
14721 if (IS_GEN5(dev)) {
14722 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14723 } else if (IS_GEN6(dev)) {
14724 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14725 } else if (IS_IVYBRIDGE(dev)) {
14726 /* FIXME: detect B0+ stepping and use auto training */
14727 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14728 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14729 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14730 if (IS_BROADWELL(dev)) {
14731 dev_priv->display.modeset_commit_cdclk =
14732 broadwell_modeset_commit_cdclk;
14733 dev_priv->display.modeset_calc_cdclk =
14734 broadwell_modeset_calc_cdclk;
14735 }
14736 } else if (IS_VALLEYVIEW(dev)) {
14737 dev_priv->display.modeset_commit_cdclk =
14738 valleyview_modeset_commit_cdclk;
14739 dev_priv->display.modeset_calc_cdclk =
14740 valleyview_modeset_calc_cdclk;
14741 } else if (IS_BROXTON(dev)) {
14742 dev_priv->display.modeset_commit_cdclk =
14743 broxton_modeset_commit_cdclk;
14744 dev_priv->display.modeset_calc_cdclk =
14745 broxton_modeset_calc_cdclk;
14746 }
14747
14748 switch (INTEL_INFO(dev)->gen) {
14749 case 2:
14750 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14751 break;
14752
14753 case 3:
14754 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14755 break;
14756
14757 case 4:
14758 case 5:
14759 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14760 break;
14761
14762 case 6:
14763 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14764 break;
14765 case 7:
14766 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14767 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14768 break;
14769 case 9:
14770 /* Drop through - unsupported since execlist only. */
14771 default:
14772 /* Default just returns -ENODEV to indicate unsupported */
14773 dev_priv->display.queue_flip = intel_default_queue_flip;
14774 }
14775
14776#ifdef __NetBSD__
14777 linux_mutex_init(&dev_priv->pps_mutex);
14778 linux_mutex_init(&dev_priv->drrs.mutex);
14779#else
14780 mutex_init(&dev_priv->pps_mutex);
14781 mutex_init(&dev_priv->drrs.mutex);
14782#endif
14783}
14784
14785/*
14786 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14787 * resume, or other times. This quirk makes sure that's the case for
14788 * affected systems.
14789 */
14790static void quirk_pipea_force(struct drm_device *dev)
14791{
14792 struct drm_i915_private *dev_priv = dev->dev_private;
14793
14794 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14795 DRM_INFO("applying pipe a force quirk\n");
14796}
14797
14798static void quirk_pipeb_force(struct drm_device *dev)
14799{
14800 struct drm_i915_private *dev_priv = dev->dev_private;
14801
14802 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14803 DRM_INFO("applying pipe b force quirk\n");
14804}
14805
14806/*
14807 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14808 */
14809static void quirk_ssc_force_disable(struct drm_device *dev)
14810{
14811 struct drm_i915_private *dev_priv = dev->dev_private;
14812 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14813 DRM_INFO("applying lvds SSC disable quirk\n");
14814}
14815
14816/*
14817 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14818 * brightness value
14819 */
14820static void quirk_invert_brightness(struct drm_device *dev)
14821{
14822 struct drm_i915_private *dev_priv = dev->dev_private;
14823 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14824 DRM_INFO("applying inverted panel brightness quirk\n");
14825}
14826
14827/* Some VBT's incorrectly indicate no backlight is present */
14828static void quirk_backlight_present(struct drm_device *dev)
14829{
14830 struct drm_i915_private *dev_priv = dev->dev_private;
14831 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14832 DRM_INFO("applying backlight present quirk\n");
14833}
14834
14835struct intel_quirk {
14836 int device;
14837 int subsystem_vendor;
14838 int subsystem_device;
14839 void (*hook)(struct drm_device *dev);
14840};
14841
14842/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14843struct intel_dmi_quirk {
14844 void (*hook)(struct drm_device *dev);
14845 const struct dmi_system_id (*dmi_id_list)[];
14846};
14847
14848static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14849{
14850 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14851 return 1;
14852}
14853
14854static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14855 {
14856 .dmi_id_list = &(const struct dmi_system_id[]) {
14857 {
14858 .callback = intel_dmi_reverse_brightness,
14859 .ident = "NCR Corporation",
14860 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14861 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14862 },
14863 },
14864 { .callback = NULL } /* terminating entry */
14865 },
14866 .hook = quirk_invert_brightness,
14867 },
14868};
14869
14870static struct intel_quirk intel_quirks[] = {
14871 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14872 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14873
14874 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14875 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14876
14877 /* 830 needs to leave pipe A & dpll A up */
14878 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14879
14880 /* 830 needs to leave pipe B & dpll B up */
14881 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14882
14883 /* Lenovo U160 cannot use SSC on LVDS */
14884 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14885
14886 /* Sony Vaio Y cannot use SSC on LVDS */
14887 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14888
14889 /* Acer Aspire 5734Z must invert backlight brightness */
14890 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14891
14892 /* Acer/eMachines G725 */
14893 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14894
14895 /* Acer/eMachines e725 */
14896 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14897
14898 /* Acer/Packard Bell NCL20 */
14899 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14900
14901 /* Acer Aspire 4736Z */
14902 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14903
14904 /* Acer Aspire 5336 */
14905 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14906
14907 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14908 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14909
14910 /* Acer C720 Chromebook (Core i3 4005U) */
14911 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14912
14913 /* Apple Macbook 2,1 (Core 2 T7400) */
14914 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14915
14916 /* Apple Macbook 4,1 */
14917 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14918
14919 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14920 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14921
14922 /* HP Chromebook 14 (Celeron 2955U) */
14923 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14924
14925 /* Dell Chromebook 11 */
14926 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14927
14928 /* Dell Chromebook 11 (2015 version) */
14929 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14930};
14931
14932static void intel_init_quirks(struct drm_device *dev)
14933{
14934 struct pci_dev *d = dev->pdev;
14935 int i;
14936
14937 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14938 struct intel_quirk *q = &intel_quirks[i];
14939
14940 if (d->device == q->device &&
14941 (d->subsystem_vendor == q->subsystem_vendor ||
14942 q->subsystem_vendor == PCI_ANY_ID) &&
14943 (d->subsystem_device == q->subsystem_device ||
14944 q->subsystem_device == PCI_ANY_ID))
14945 q->hook(dev);
14946 }
14947 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14948 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14949 intel_dmi_quirks[i].hook(dev);
14950 }
14951}
14952
14953/* Disable the VGA plane that we never use */
14954void i915_disable_vga(struct drm_device *dev)
14955{
14956 struct drm_i915_private *dev_priv = dev->dev_private;
14957 u8 sr1;
14958 u32 vga_reg = i915_vgacntrl_reg(dev);
14959
14960#ifdef __NetBSD__
14961 {
14962 const bus_addr_t vgabase = 0x3c0;
14963 const bus_space_tag_t iot = dev->pdev->pd_pa.pa_iot;
14964 bus_space_handle_t ioh;
14965 int error;
14966
14967 error = bus_space_map(iot, vgabase, 0x10, 0, &ioh);
14968 if (error) {
14969 aprint_error_dev(dev->pdev->pd_dev,
14970 "unable to map VGA registers: %d\n", error);
14971 } else {
14972 CTASSERT(vgabase <= VGA_SR_INDEX);
14973 CTASSERT(vgabase <= VGA_SR_DATA);
14974 bus_space_write_1(iot, ioh, VGA_SR_INDEX - vgabase, SR01);
14975 sr1 = bus_space_read_1(iot, ioh, VGA_SR_DATA - vgabase);
14976 bus_space_write_1(iot, ioh, VGA_SR_DATA - vgabase,
14977 (sr1 | __BIT(5)));
14978 bus_space_unmap(iot, ioh, 0x10);
14979 }
14980 }
14981#else
14982 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14983 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14984 outb(SR01, VGA_SR_INDEX);
14985 sr1 = inb(VGA_SR_DATA);
14986 outb(sr1 | 1<<5, VGA_SR_DATA);
14987 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14988#endif
14989 udelay(300);
14990
14991 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14992 POSTING_READ(vga_reg);
14993}
14994
14995void intel_modeset_init_hw(struct drm_device *dev)
14996{
14997 intel_update_cdclk(dev);
14998 intel_prepare_ddi(dev);
14999 intel_init_clock_gating(dev);
15000 intel_enable_gt_powersave(dev);
15001}
15002
15003void intel_modeset_init(struct drm_device *dev)
15004{
15005 struct drm_i915_private *dev_priv = dev->dev_private;
15006 int sprite, ret;
15007 enum i915_pipe pipe;
15008 struct intel_crtc *crtc;
15009
15010 drm_mode_config_init(dev);
15011
15012 dev->mode_config.min_width = 0;
15013 dev->mode_config.min_height = 0;
15014
15015 dev->mode_config.preferred_depth = 24;
15016 dev->mode_config.prefer_shadow = 1;
15017
15018 dev->mode_config.allow_fb_modifiers = true;
15019
15020 dev->mode_config.funcs = &intel_mode_funcs;
15021
15022 intel_init_quirks(dev);
15023
15024 intel_init_pm(dev);
15025
15026 if (INTEL_INFO(dev)->num_pipes == 0)
15027 return;
15028
15029 /*
15030 * There may be no VBT; and if the BIOS enabled SSC we can
15031 * just keep using it to avoid unnecessary flicker. Whereas if the
15032 * BIOS isn't using it, don't assume it will work even if the VBT
15033 * indicates as much.
15034 */
15035 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15036 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15037 DREF_SSC1_ENABLE);
15038
15039 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15040 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15041 bios_lvds_use_ssc ? "en" : "dis",
15042 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15043 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15044 }
15045 }
15046
15047 intel_init_display(dev);
15048 intel_init_audio(dev);
15049
15050 if (IS_GEN2(dev)) {
15051 dev->mode_config.max_width = 2048;
15052 dev->mode_config.max_height = 2048;
15053 } else if (IS_GEN3(dev)) {
15054 dev->mode_config.max_width = 4096;
15055 dev->mode_config.max_height = 4096;
15056 } else {
15057 dev->mode_config.max_width = 8192;
15058 dev->mode_config.max_height = 8192;
15059 }
15060
15061 if (IS_845G(dev) || IS_I865G(dev)) {
15062 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15063 dev->mode_config.cursor_height = 1023;
15064 } else if (IS_GEN2(dev)) {
15065 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15066 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15067 } else {
15068 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15069 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15070 }
15071
15072 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15073
15074 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15075 INTEL_INFO(dev)->num_pipes,
15076 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15077
15078 for_each_pipe(dev_priv, pipe) {
15079 intel_crtc_init(dev, pipe);
15080 for_each_sprite(dev_priv, pipe, sprite) {
15081 ret = intel_plane_init(dev, pipe, sprite);
15082 if (ret)
15083 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15084 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15085 }
15086 }
15087
15088 intel_update_czclk(dev_priv);
15089 intel_update_cdclk(dev);
15090
15091 intel_shared_dpll_init(dev);
15092
15093#ifndef __NetBSD__ /* XXX We wait until intelfb is ready. */
15094 /* Just disable it once at startup */
15095 i915_disable_vga(dev);
15096#endif
15097 intel_setup_outputs(dev);
15098
15099 /* Just in case the BIOS is doing something questionable. */
15100 intel_fbc_disable(dev_priv);
15101
15102 drm_modeset_lock_all(dev);
15103 intel_modeset_setup_hw_state(dev);
15104 drm_modeset_unlock_all(dev);
15105
15106 for_each_intel_crtc(dev, crtc) {
15107 struct intel_initial_plane_config plane_config = {};
15108
15109 if (!crtc->active)
15110 continue;
15111
15112 /*
15113 * Note that reserving the BIOS fb up front prevents us
15114 * from stuffing other stolen allocations like the ring
15115 * on top. This prevents some ugliness at boot time, and
15116 * can even allow for smooth boot transitions if the BIOS
15117 * fb is large enough for the active pipe configuration.
15118 */
15119 dev_priv->display.get_initial_plane_config(crtc,
15120 &plane_config);
15121
15122 /*
15123 * If the fb is shared between multiple heads, we'll
15124 * just get the first one.
15125 */
15126 intel_find_initial_plane_obj(crtc, &plane_config);
15127 }
15128}
15129
15130static void intel_enable_pipe_a(struct drm_device *dev)
15131{
15132 struct intel_connector *connector;
15133 struct drm_connector *crt = NULL;
15134 struct intel_load_detect_pipe load_detect_temp;
15135 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15136
15137 /* We can't just switch on the pipe A, we need to set things up with a
15138 * proper mode and output configuration. As a gross hack, enable pipe A
15139 * by enabling the load detect pipe once. */
15140 for_each_intel_connector(dev, connector) {
15141 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15142 crt = &connector->base;
15143 break;
15144 }
15145 }
15146
15147 if (!crt)
15148 return;
15149
15150 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15151 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15152}
15153
15154static bool
15155intel_check_plane_mapping(struct intel_crtc *crtc)
15156{
15157 struct drm_device *dev = crtc->base.dev;
15158 struct drm_i915_private *dev_priv = dev->dev_private;
15159 u32 val;
15160
15161 if (INTEL_INFO(dev)->num_pipes == 1)
15162 return true;
15163
15164 val = I915_READ(DSPCNTR(!crtc->plane));
15165
15166 if ((val & DISPLAY_PLANE_ENABLE) &&
15167 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15168 return false;
15169
15170 return true;
15171}
15172
15173static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15174{
15175 struct drm_device *dev = crtc->base.dev;
15176 struct intel_encoder *encoder;
15177
15178 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15179 return true;
15180
15181 return false;
15182}
15183
15184static void intel_sanitize_crtc(struct intel_crtc *crtc)
15185{
15186 struct drm_device *dev = crtc->base.dev;
15187 struct drm_i915_private *dev_priv = dev->dev_private;
15188 u32 reg;
15189
15190 /* Clear any frame start delays used for debugging left by the BIOS */
15191 reg = PIPECONF(crtc->config->cpu_transcoder);
15192 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15193
15194 /* restore vblank interrupts to correct state */
15195 drm_crtc_vblank_reset(&crtc->base);
15196 if (crtc->active) {
15197 struct intel_plane *plane;
15198
15199 drm_crtc_vblank_on(&crtc->base);
15200
15201 /* Disable everything but the primary plane */
15202 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15203 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15204 continue;
15205
15206 plane->disable_plane(&plane->base, &crtc->base);
15207 }
15208 }
15209
15210 /* We need to sanitize the plane -> pipe mapping first because this will
15211 * disable the crtc (and hence change the state) if it is wrong. Note
15212 * that gen4+ has a fixed plane -> pipe mapping. */
15213 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15214 bool plane;
15215
15216 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15217 crtc->base.base.id);
15218
15219 /* Pipe has the wrong plane attached and the plane is active.
15220 * Temporarily change the plane mapping and disable everything
15221 * ... */
15222 plane = crtc->plane;
15223 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15224 crtc->plane = !plane;
15225 intel_crtc_disable_noatomic(&crtc->base);
15226 crtc->plane = plane;
15227 }
15228
15229 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15230 crtc->pipe == PIPE_A && !crtc->active) {
15231 /* BIOS forgot to enable pipe A, this mostly happens after
15232 * resume. Force-enable the pipe to fix this, the update_dpms
15233 * call below we restore the pipe to the right state, but leave
15234 * the required bits on. */
15235 intel_enable_pipe_a(dev);
15236 }
15237
15238 /* Adjust the state of the output pipe according to whether we
15239 * have active connectors/encoders. */
15240 if (!intel_crtc_has_encoders(crtc))
15241 intel_crtc_disable_noatomic(&crtc->base);
15242
15243 if (crtc->active != crtc->base.state->active) {
15244 struct intel_encoder *encoder;
15245
15246 /* This can happen either due to bugs in the get_hw_state
15247 * functions or because of calls to intel_crtc_disable_noatomic,
15248 * or because the pipe is force-enabled due to the
15249 * pipe A quirk. */
15250 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15251 crtc->base.base.id,
15252 crtc->base.state->enable ? "enabled" : "disabled",
15253 crtc->active ? "enabled" : "disabled");
15254
15255 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15256 crtc->base.state->active = crtc->active;
15257 crtc->base.enabled = crtc->active;
15258
15259 /* Because we only establish the connector -> encoder ->
15260 * crtc links if something is active, this means the
15261 * crtc is now deactivated. Break the links. connector
15262 * -> encoder links are only establish when things are
15263 * actually up, hence no need to break them. */
15264 WARN_ON(crtc->active);
15265
15266 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15267 encoder->base.crtc = NULL;
15268 }
15269
15270 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15271 /*
15272 * We start out with underrun reporting disabled to avoid races.
15273 * For correct bookkeeping mark this on active crtcs.
15274 *
15275 * Also on gmch platforms we dont have any hardware bits to
15276 * disable the underrun reporting. Which means we need to start
15277 * out with underrun reporting disabled also on inactive pipes,
15278 * since otherwise we'll complain about the garbage we read when
15279 * e.g. coming up after runtime pm.
15280 *
15281 * No protection against concurrent access is required - at
15282 * worst a fifo underrun happens which also sets this to false.
15283 */
15284 crtc->cpu_fifo_underrun_disabled = true;
15285 crtc->pch_fifo_underrun_disabled = true;
15286 }
15287}
15288
15289static void intel_sanitize_encoder(struct intel_encoder *encoder)
15290{
15291 struct intel_connector *connector;
15292 struct drm_device *dev = encoder->base.dev;
15293 bool active = false;
15294
15295 /* We need to check both for a crtc link (meaning that the
15296 * encoder is active and trying to read from a pipe) and the
15297 * pipe itself being active. */
15298 bool has_active_crtc = encoder->base.crtc &&
15299 to_intel_crtc(encoder->base.crtc)->active;
15300
15301 for_each_intel_connector(dev, connector) {
15302 if (connector->base.encoder != &encoder->base)
15303 continue;
15304
15305 active = true;
15306 break;
15307 }
15308
15309 if (active && !has_active_crtc) {
15310 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15311 encoder->base.base.id,
15312 encoder->base.name);
15313
15314 /* Connector is active, but has no active pipe. This is
15315 * fallout from our resume register restoring. Disable
15316 * the encoder manually again. */
15317 if (encoder->base.crtc) {
15318 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15319 encoder->base.base.id,
15320 encoder->base.name);
15321 encoder->disable(encoder);
15322 if (encoder->post_disable)
15323 encoder->post_disable(encoder);
15324 }
15325 encoder->base.crtc = NULL;
15326
15327 /* Inconsistent output/port/pipe state happens presumably due to
15328 * a bug in one of the get_hw_state functions. Or someplace else
15329 * in our code, like the register restore mess on resume. Clamp
15330 * things to off as a safer default. */
15331 for_each_intel_connector(dev, connector) {
15332 if (connector->encoder != encoder)
15333 continue;
15334 connector->base.dpms = DRM_MODE_DPMS_OFF;
15335 connector->base.encoder = NULL;
15336 }
15337 }
15338 /* Enabled encoders without active connectors will be fixed in
15339 * the crtc fixup. */
15340}
15341
15342void i915_redisable_vga_power_on(struct drm_device *dev)
15343{
15344 struct drm_i915_private *dev_priv = dev->dev_private;
15345 u32 vga_reg = i915_vgacntrl_reg(dev);
15346
15347 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15348 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15349 i915_disable_vga(dev);
15350 }
15351}
15352
15353void i915_redisable_vga(struct drm_device *dev)
15354{
15355 struct drm_i915_private *dev_priv = dev->dev_private;
15356
15357 /* This function can be called both from intel_modeset_setup_hw_state or
15358 * at a very early point in our resume sequence, where the power well
15359 * structures are not yet restored. Since this function is at a very
15360 * paranoid "someone might have enabled VGA while we were not looking"
15361 * level, just check if the power well is enabled instead of trying to
15362 * follow the "don't touch the power well if we don't need it" policy
15363 * the rest of the driver uses. */
15364 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15365 return;
15366
15367 i915_redisable_vga_power_on(dev);
15368}
15369
15370static bool primary_get_hw_state(struct intel_plane *plane)
15371{
15372 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15373
15374 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15375}
15376
15377/* FIXME read out full plane state for all planes */
15378static void readout_plane_state(struct intel_crtc *crtc)
15379{
15380 struct drm_plane *primary = crtc->base.primary;
15381 struct intel_plane_state *plane_state =
15382 to_intel_plane_state(primary->state);
15383
15384 plane_state->visible =
15385 primary_get_hw_state(to_intel_plane(primary));
15386
15387 if (plane_state->visible)
15388 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15389}
15390
15391static void intel_modeset_readout_hw_state(struct drm_device *dev)
15392{
15393 struct drm_i915_private *dev_priv = dev->dev_private;
15394 enum i915_pipe pipe;
15395 struct intel_crtc *crtc;
15396 struct intel_encoder *encoder;
15397 struct intel_connector *connector;
15398 int i;
15399
15400 for_each_intel_crtc(dev, crtc) {
15401 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15402 memset(crtc->config, 0, sizeof(*crtc->config));
15403 crtc->config->base.crtc = &crtc->base;
15404
15405 crtc->active = dev_priv->display.get_pipe_config(crtc,
15406 crtc->config);
15407
15408 crtc->base.state->active = crtc->active;
15409 crtc->base.enabled = crtc->active;
15410
15411 readout_plane_state(crtc);
15412
15413 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15414 crtc->base.base.id,
15415 crtc->active ? "enabled" : "disabled");
15416 }
15417
15418 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15419 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15420
15421 pll->on = pll->get_hw_state(dev_priv, pll,
15422 &pll->config.hw_state);
15423 pll->active = 0;
15424 pll->config.crtc_mask = 0;
15425 for_each_intel_crtc(dev, crtc) {
15426 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15427 pll->active++;
15428 pll->config.crtc_mask |= 1 << crtc->pipe;
15429 }
15430 }
15431
15432 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15433 pll->name, pll->config.crtc_mask, pll->on);
15434
15435 if (pll->config.crtc_mask)
15436 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15437 }
15438
15439 for_each_intel_encoder(dev, encoder) {
15440 pipe = 0;
15441
15442 if (encoder->get_hw_state(encoder, &pipe)) {
15443 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15444 encoder->base.crtc = &crtc->base;
15445 encoder->get_config(encoder, crtc->config);
15446 } else {
15447 encoder->base.crtc = NULL;
15448 }
15449
15450 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15451 encoder->base.base.id,
15452 encoder->base.name,
15453 encoder->base.crtc ? "enabled" : "disabled",
15454 pipe_name(pipe));
15455 }
15456
15457 for_each_intel_connector(dev, connector) {
15458 if (connector->get_hw_state(connector)) {
15459 connector->base.dpms = DRM_MODE_DPMS_ON;
15460 connector->base.encoder = &connector->encoder->base;
15461 } else {
15462 connector->base.dpms = DRM_MODE_DPMS_OFF;
15463 connector->base.encoder = NULL;
15464 }
15465 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15466 connector->base.base.id,
15467 connector->base.name,
15468 connector->base.encoder ? "enabled" : "disabled");
15469 }
15470
15471 for_each_intel_crtc(dev, crtc) {
15472 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15473
15474 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15475 if (crtc->base.state->active) {
15476 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15477 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15478 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15479
15480 /*
15481 * The initial mode needs to be set in order to keep
15482 * the atomic core happy. It wants a valid mode if the
15483 * crtc's enabled, so we do the above call.
15484 *
15485 * At this point some state updated by the connectors
15486 * in their ->detect() callback has not run yet, so
15487 * no recalculation can be done yet.
15488 *
15489 * Even if we could do a recalculation and modeset
15490 * right now it would cause a double modeset if
15491 * fbdev or userspace chooses a different initial mode.
15492 *
15493 * If that happens, someone indicated they wanted a
15494 * mode change, which means it's safe to do a full
15495 * recalculation.
15496 */
15497 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15498
15499 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15500 update_scanline_offset(crtc);
15501 }
15502 }
15503}
15504
15505/* Scan out the current hw modeset state,
15506 * and sanitizes it to the current state
15507 */
15508static void
15509intel_modeset_setup_hw_state(struct drm_device *dev)
15510{
15511 struct drm_i915_private *dev_priv = dev->dev_private;
15512 enum i915_pipe pipe;
15513 struct intel_crtc *crtc;
15514 struct intel_encoder *encoder;
15515 int i;
15516
15517 intel_modeset_readout_hw_state(dev);
15518
15519 /* HW state is read out, now we need to sanitize this mess. */
15520 for_each_intel_encoder(dev, encoder) {
15521 intel_sanitize_encoder(encoder);
15522 }
15523
15524 for_each_pipe(dev_priv, pipe) {
15525 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15526 intel_sanitize_crtc(crtc);
15527 intel_dump_pipe_config(crtc, crtc->config,
15528 "[setup_hw_state]");
15529 }
15530
15531 intel_modeset_update_connector_atomic_state(dev);
15532
15533 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15534 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15535
15536 if (!pll->on || pll->active)
15537 continue;
15538
15539 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15540
15541 pll->disable(dev_priv, pll);
15542 pll->on = false;
15543 }
15544
15545 if (IS_VALLEYVIEW(dev))
15546 vlv_wm_get_hw_state(dev);
15547 else if (IS_GEN9(dev))
15548 skl_wm_get_hw_state(dev);
15549 else if (HAS_PCH_SPLIT(dev))
15550 ilk_wm_get_hw_state(dev);
15551
15552 for_each_intel_crtc(dev, crtc) {
15553 unsigned long put_domains;
15554
15555 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15556 if (WARN_ON(put_domains))
15557 modeset_put_power_domains(dev_priv, put_domains);
15558 }
15559 intel_display_set_init_power(dev_priv, false);
15560}
15561
15562void intel_display_resume(struct drm_device *dev)
15563{
15564 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15565 struct intel_connector *conn;
15566 struct intel_plane *plane;
15567 struct drm_crtc *crtc;
15568 int ret;
15569
15570 if (!state)
15571 return;
15572
15573 state->acquire_ctx = dev->mode_config.acquire_ctx;
15574
15575 /* preserve complete old state, including dpll */
15576 intel_atomic_get_shared_dpll_state(state);
15577
15578 for_each_crtc(dev, crtc) {
15579 struct drm_crtc_state *crtc_state =
15580 drm_atomic_get_crtc_state(state, crtc);
15581
15582 ret = PTR_ERR_OR_ZERO(crtc_state);
15583 if (ret)
15584 goto err;
15585
15586 /* force a restore */
15587 crtc_state->mode_changed = true;
15588 }
15589
15590 for_each_intel_plane(dev, plane) {
15591 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15592 if (ret)
15593 goto err;
15594 }
15595
15596 for_each_intel_connector(dev, conn) {
15597 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15598 if (ret)
15599 goto err;
15600 }
15601
15602 intel_modeset_setup_hw_state(dev);
15603
15604 i915_redisable_vga(dev);
15605 ret = drm_atomic_commit(state);
15606 if (!ret)
15607 return;
15608
15609err:
15610 DRM_ERROR("Restoring old state failed with %i\n", ret);
15611 drm_atomic_state_free(state);
15612}
15613
15614void intel_modeset_gem_init(struct drm_device *dev)
15615{
15616 struct drm_crtc *c;
15617 struct drm_i915_gem_object *obj;
15618 int ret;
15619
15620 mutex_lock(&dev->struct_mutex);
15621 intel_init_gt_powersave(dev);
15622 mutex_unlock(&dev->struct_mutex);
15623
15624 intel_modeset_init_hw(dev);
15625
15626 intel_setup_overlay(dev);
15627
15628 /*
15629 * Make sure any fbs we allocated at startup are properly
15630 * pinned & fenced. When we do the allocation it's too early
15631 * for this.
15632 */
15633 for_each_crtc(dev, c) {
15634 obj = intel_fb_obj(c->primary->fb);
15635 if (obj == NULL)
15636 continue;
15637
15638 mutex_lock(&dev->struct_mutex);
15639 ret = intel_pin_and_fence_fb_obj(c->primary,
15640 c->primary->fb,
15641 c->primary->state,
15642 NULL, NULL);
15643 mutex_unlock(&dev->struct_mutex);
15644 if (ret) {
15645 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15646 to_intel_crtc(c)->pipe);
15647 drm_framebuffer_unreference(c->primary->fb);
15648 c->primary->fb = NULL;
15649 c->primary->crtc = c->primary->state->crtc = NULL;
15650 update_state_fb(c->primary);
15651 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15652 }
15653 }
15654
15655 intel_backlight_register(dev);
15656}
15657
15658void intel_connector_unregister(struct intel_connector *intel_connector)
15659{
15660 struct drm_connector *connector = &intel_connector->base;
15661
15662 intel_panel_destroy_backlight(connector);
15663 drm_connector_unregister(connector);
15664}
15665
15666void intel_modeset_cleanup(struct drm_device *dev)
15667{
15668 struct drm_i915_private *dev_priv = dev->dev_private;
15669 struct drm_connector *connector;
15670
15671 intel_disable_gt_powersave(dev);
15672
15673 intel_backlight_unregister(dev);
15674
15675 /*
15676 * Interrupts and polling as the first thing to avoid creating havoc.
15677 * Too much stuff here (turning of connectors, ...) would
15678 * experience fancy races otherwise.
15679 */
15680 intel_irq_uninstall(dev_priv);
15681
15682 /*
15683 * Due to the hpd irq storm handling the hotplug work can re-arm the
15684 * poll handlers. Hence disable polling after hpd handling is shut down.
15685 */
15686 drm_kms_helper_poll_fini(dev);
15687
15688 intel_unregister_dsm_handler();
15689
15690 intel_fbc_disable(dev_priv);
15691
15692 /* flush any delayed tasks or pending work */
15693 flush_scheduled_work();
15694
15695 /* destroy the backlight and sysfs files before encoders/connectors */
15696 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15697 struct intel_connector *intel_connector;
15698
15699 intel_connector = to_intel_connector(connector);
15700 intel_connector->unregister(intel_connector);
15701 }
15702
15703 drm_mode_config_cleanup(dev);
15704
15705 intel_cleanup_overlay(dev);
15706
15707 mutex_lock(&dev->struct_mutex);
15708 intel_cleanup_gt_powersave(dev);
15709 mutex_unlock(&dev->struct_mutex);
15710
15711 intel_teardown_gmbus(dev);
15712
15713#ifdef __NetBSD__
15714 linux_mutex_destroy(&dev_priv->psr.lock);
15715 linux_mutex_destroy(&dev_priv->drrs.mutex);
15716 linux_mutex_destroy(&dev_priv->pps_mutex);
15717 linux_mutex_destroy(&dev_priv->fbc.lock);
15718#else
15719 mutex_destroy(&dev_priv->psr.lock);
15720 mutex_destroy(&dev_priv->drrs.mutex);
15721 mutex_destroy(&dev_priv->pps_mutex);
15722 mutex_destroy(&dev_priv->fbc.lock);
15723#endif
15724}
15725
15726/*
15727 * Return which encoder is currently attached for connector.
15728 */
15729struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15730{
15731 return &intel_attached_encoder(connector)->base;
15732}
15733
15734void intel_connector_attach_encoder(struct intel_connector *connector,
15735 struct intel_encoder *encoder)
15736{
15737 connector->encoder = encoder;
15738 drm_mode_connector_attach_encoder(&connector->base,
15739 &encoder->base);
15740}
15741
15742/*
15743 * set vga decode state - true == enable VGA decode
15744 */
15745int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15746{
15747 struct drm_i915_private *dev_priv = dev->dev_private;
15748 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15749 u16 gmch_ctrl;
15750
15751 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15752 DRM_ERROR("failed to read control word\n");
15753 return -EIO;
15754 }
15755
15756 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15757 return 0;
15758
15759 if (state)
15760 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15761 else
15762 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15763
15764 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15765 DRM_ERROR("failed to write control word\n");
15766 return -EIO;
15767 }
15768
15769 return 0;
15770}
15771
15772struct intel_display_error_state {
15773
15774 u32 power_well_driver;
15775
15776 int num_transcoders;
15777
15778 struct intel_cursor_error_state {
15779 u32 control;
15780 u32 position;
15781 u32 base;
15782 u32 size;
15783 } cursor[I915_MAX_PIPES];
15784
15785 struct intel_pipe_error_state {
15786 bool power_domain_on;
15787 u32 source;
15788 u32 stat;
15789 } pipe[I915_MAX_PIPES];
15790
15791 struct intel_plane_error_state {
15792 u32 control;
15793 u32 stride;
15794 u32 size;
15795 u32 pos;
15796 u32 addr;
15797 u32 surface;
15798 u32 tile_offset;
15799 } plane[I915_MAX_PIPES];
15800
15801 struct intel_transcoder_error_state {
15802 bool power_domain_on;
15803 enum transcoder cpu_transcoder;
15804
15805 u32 conf;
15806
15807 u32 htotal;
15808 u32 hblank;
15809 u32 hsync;
15810 u32 vtotal;
15811 u32 vblank;
15812 u32 vsync;
15813 } transcoder[4];
15814};
15815
15816struct intel_display_error_state *
15817intel_display_capture_error_state(struct drm_device *dev)
15818{
15819 struct drm_i915_private *dev_priv = dev->dev_private;
15820 struct intel_display_error_state *error;
15821 int transcoders[] = {
15822 TRANSCODER_A,
15823 TRANSCODER_B,
15824 TRANSCODER_C,
15825 TRANSCODER_EDP,
15826 };
15827 int i;
15828
15829 if (INTEL_INFO(dev)->num_pipes == 0)
15830 return NULL;
15831
15832 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15833 if (error == NULL)
15834 return NULL;
15835
15836 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15837 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15838
15839 for_each_pipe(dev_priv, i) {
15840 error->pipe[i].power_domain_on =
15841 __intel_display_power_is_enabled(dev_priv,
15842 POWER_DOMAIN_PIPE(i));
15843 if (!error->pipe[i].power_domain_on)
15844 continue;
15845
15846 error->cursor[i].control = I915_READ(CURCNTR(i));
15847 error->cursor[i].position = I915_READ(CURPOS(i));
15848 error->cursor[i].base = I915_READ(CURBASE(i));
15849
15850 error->plane[i].control = I915_READ(DSPCNTR(i));
15851 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15852 if (INTEL_INFO(dev)->gen <= 3) {
15853 error->plane[i].size = I915_READ(DSPSIZE(i));
15854 error->plane[i].pos = I915_READ(DSPPOS(i));
15855 }
15856 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15857 error->plane[i].addr = I915_READ(DSPADDR(i));
15858 if (INTEL_INFO(dev)->gen >= 4) {
15859 error->plane[i].surface = I915_READ(DSPSURF(i));
15860 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15861 }
15862
15863 error->pipe[i].source = I915_READ(PIPESRC(i));
15864
15865 if (HAS_GMCH_DISPLAY(dev))
15866 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15867 }
15868
15869 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15870 if (HAS_DDI(dev_priv->dev))
15871 error->num_transcoders++; /* Account for eDP. */
15872
15873 for (i = 0; i < error->num_transcoders; i++) {
15874 enum transcoder cpu_transcoder = transcoders[i];
15875
15876 error->transcoder[i].power_domain_on =
15877 __intel_display_power_is_enabled(dev_priv,
15878 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15879 if (!error->transcoder[i].power_domain_on)
15880 continue;
15881
15882 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15883
15884 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15885 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15886 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15887 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15888 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15889 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15890 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15891 }
15892
15893 return error;
15894}
15895
15896#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15897
15898void
15899intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15900 struct drm_device *dev,
15901 struct intel_display_error_state *error)
15902{
15903 struct drm_i915_private *dev_priv = dev->dev_private;
15904 int i;
15905
15906 if (!error)
15907 return;
15908
15909 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15910 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15911 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15912 error->power_well_driver);
15913 for_each_pipe(dev_priv, i) {
15914 err_printf(m, "Pipe [%d]:\n", i);
15915 err_printf(m, " Power: %s\n",
15916 error->pipe[i].power_domain_on ? "on" : "off");
15917 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15918 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15919
15920 err_printf(m, "Plane [%d]:\n", i);
15921 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15922 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15923 if (INTEL_INFO(dev)->gen <= 3) {
15924 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15925 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15926 }
15927 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15928 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15929 if (INTEL_INFO(dev)->gen >= 4) {
15930 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15931 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15932 }
15933
15934 err_printf(m, "Cursor [%d]:\n", i);
15935 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15936 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15937 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15938 }
15939
15940 for (i = 0; i < error->num_transcoders; i++) {
15941 err_printf(m, "CPU transcoder: %c\n",
15942 transcoder_name(error->transcoder[i].cpu_transcoder));
15943 err_printf(m, " Power: %s\n",
15944 error->transcoder[i].power_domain_on ? "on" : "off");
15945 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15946 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15947 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15948 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15949 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15950 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15951 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15952 }
15953}
15954
15955void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15956{
15957 struct intel_crtc *crtc;
15958
15959 for_each_intel_crtc(dev, crtc) {
15960 struct intel_unpin_work *work;
15961
15962 spin_lock_irq(&dev->event_lock);
15963
15964 work = crtc->unpin_work;
15965
15966 if (work && work->event &&
15967 work->event->base.file_priv == file) {
15968 kfree(work->event);
15969 work->event = NULL;
15970 }
15971
15972 spin_unlock_irq(&dev->event_lock);
15973 }
15974}
15975